S6B0794 Ver la hoja de datos (PDF) - Samsung
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S6B0794 Datasheet PDF : 31 Pages
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S6B0794 SPEC. VER 3.0
160 SEG / COM DRIVER FOR STN LCD
PIN FUNCTION
Segment Mode
Symbol
Function
VDD
Logic system power supply pin connects to +2.4 to +5.5V
VSS
Ground pin connects to 0 V
V0R, V0L
V12R , V12L
V43R , V43L
Power supply pin for LC driver voltage bias.
. Normally, the bias voltage used is set by a resistor divider.
. Ensure that voltage are set such that VSS<V43<V12<V0.
. To further reduce the difference between the output waveforms of LC driver
output pins Y1 and Y160, externally connect ViR and ViL(i=0, 12, 43)
Input pin for display data
. In 4-bit parallel input mode, input data into the 4 pins DI0 – DI3.
DI0 – DI7
Connect DI4 – DI7 to VSS or VDD.
. In 8-bit parallel input mode, input data into the 8 pins DI0 – DI7.
XCK
Clock input pin for taking display data
. Data is read on the falling edge of the clock pulse.
Latch pulse input pin for display data
LP
. Data is latched on the falling edge of the clock pulse.
Direction selection pin for reading display data
L/R
. When set to VSS level “L”, data is read sequentially from Y160 to Y1.
. When set to VDD level H”, data is read sequentially from Y1 to Y160.
Control input pin for output deselect level
. The input signal is level-shifted from logic voltage level to LC drive voltage
level, and controls LC drive circuit.
. When set to VSS level “L”, the LC drive output pins (Y1-Y160) are set to level
VSS.
DISPOFFB
. While set to “L”, the contents of the line latch are reset, but read the display
data in the data latch regardless of condition of DISPOFFB.
When the DISPOFFB function is canceled, the driver outputs deselect
level(V12 or V43), then outputs the contents of the data latch on the next
falling edge of the LP. That time, if DISPOFFB removal time can not keep
regulation what is shown AC characteristics (page 21), can not output the
reading data correctly.
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