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FBL2031BB

9-bit BTL 3.3V latched/registered/pass-thru Futurebus+ transceiver

Philips Electronics 

Philips Semiconductors

9-bit BTL 3.3V latched/registered/pass-thru

Futurebus+ transceiver

Product specification

FBL2031

AC ELECTRICAL CHARACTERISTICS

A TO B 16.5 Ω LOAD SPECIFICATIONS

SYMBOL

PARAMETER

TEST

CONDITION

Tamb = +25°C,

VCC = 3.3V,

MIN TYP MAX

Tamb = –40 to +85°C,

VCC = 3.3V±10%,

MIN

MAX

UNIT

tPLH

Propagation delay (thru latch)

tPHL

An to Bn

Waveform 1, 2

1.4

2.7

3.9

1.2

2.4

3.6

1.0

1.0

5.0

4.0

ns

tPLH

Propagation delay (transparent latch)

tPHL

An to Bn

Waveform 1, 2

1.8

3.0

4.2

2.0

3.2

4.7

1.0

1.4

5.6

5.5

ns

tPLH

Propagation delay

tPHL

LCAB to Bn (latch)

Waveform 1, 2

8.6

11.4 14.2

6.5

8.0 10.6 13.3

6.4

17.5

16.1

ns

tPLH

Propagation delay

tPHL

LCAB to Bn (register)

Waveform 1, 2

2.2

3.5

4.8

2.3

3.7

5.1

1.2

1.7

6.1

5.9

ns

tPLH

Propagation delay

tPHL

SEL0 or SEL1 to Bn (inverting)

Waveform 1, 2

2.6

4.5

6.7

1.4

4.4

7.7

1.5

1.1

8.1

8.4

ns

tPLH

Propagation delay

tPHL

SEL0 or SEL1 to Bn (non-inverting)

Waveform 1, 2

2.2

4.5

6.9

2.3

4.0

5.8

1.4

1.5

8.2

6.9

ns

tPLH

tPHL

OEB0 to Bn

Waveform 1, 2

1.8

3.1

4.4

1.7

2.9

4.2

1.0

1.0

5.8

6.0

ns

tTLH

Output transition time, Bn Port

tTHL

(1.3V to 1.8V)

Test Circuit and

Waveforms

1.2

0.4

3.0

1.5

ns

tSK(o)

Output to output skew for multiple

channels1

Waveform 3

0.5

1.0

2.0

ns

tSK(p)

Pulse skew2

 tPHL – tPLH  MAX

Waveform 2

0.5

1.0

1.5

ns

NOTES:

1.  tPNactual – tPMactual for any data input to output path compared to any other data input to output path where N and M are either LH or

HL. Skew times are valid only under same test conditions (temperature, VCC, loading, etc.). tSK (0) compares tPLH on a given path to tPLH

on any other path or compares tPHL on a given path to tPHL on any other path.

2. tSK(p) is used to quantify duty cycle characteristics. In essence it compares the input signal duty cycle to the corresponding output signal

duty cycle (50MHz input frequency and 50% duty cycle, tested on data paths only).

2000 Apr 18

11

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