datasheetbank_Logo
búsqueda de Hoja de datos y gratuito Fichas de descarga

MC74HC280 Ver la hoja de datos (PDF) - Motorola => Freescale

Número de pieza
componentes Descripción
Lista de partido
MC74HC280
Motorola
Motorola => Freescale Motorola
MC74HC280 Datasheet PDF : 6 Pages
1 2 3 4 5 6
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ AC ELECTRICAL CHARACTERISTICS (CL = 50 pF, Input tr = tf = 6 ns)
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ Symbol
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ tPLH,
tPHL
Parameter
Maximum Propagation Delay, Data Inputs to Parity Outputs
(Figures 1 and 2)
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ tTLH,
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ tTHL
Maximum Output Transition Time, Any Output
(Figures 1 and 2)
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ Cin
Maximum Input Capacitance
MC74HC280
VCC
V
2.0
4.5
6.0
2.0
4.5
6.0
Guaranteed Limit
v v – 55 to
25_C
85_C
125_C Unit
205
255
310
ns
41
51
62
35
43
53
75
95
110
ns
15
19
22
13
16
19
10
10
10
pF
NOTES:
1. For propagation delays with loads other than 50 pF, see Chapter 2 of the Motorola High–Speed CMOS Data Book (DL129/D).
2. Information on typical parametric values can be found in Chapter 2 of the Motorola High–Speed CMOS Data Book (DL129/D).
Typical @ 25°C, VCC = 5.0 V
CPD
Power Dissipation Capacitance (Per Package)*
60
pF
* Used to determine the no–load dynamic power consumption: PD = CPD VCC2f + ICC VCC. For load considerations, see Chapter 2 of the
Motorola High–Speed CMOS Data Book (DL129/D).
PIN DESCRIPTIONS
INPUTS
A, B, C, D, E, F, G, H, I (Pins 8 – 13, 1, 2, 4)
Nine–bit data–word inputs. The data word placed on these
pins is checked for even or odd parity.
OUTPUTS
Even Parity (Pin 5)
Even–parity output. This pin goes high if the data word has
even parity and low if the data word has odd parity.
Odd Parity (Pin 6)
Odd–parity output. This pin goes high if the data word has
odd parity and low if the data word has even parity.
tr
DATA INPUT
tPLH
PARITY OUTPUT
90%
50%
10%
90%
50%
10%
tTLH
tf
VCC
GND
tPHL
tTHL
Figure 1. Switching Waveforms
DEVICE
UNDER
TEST
TEST POINT
OUTPUT
CL*
* Includes all probe and jig capacitance
Figure 2. Test Circuit
High–Speed CMOS Logic Data
3
DL129 — Rev 6
MOTOROLA

Share Link: 

datasheetbank.com [ Privacy Policy ] [ Request Datasheet ] [ Contact Us ]