SA7026 Ver la hoja de datos (PDF) - Philips Electronics
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SA7026 Datasheet PDF : 18 Pages
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Philips Semiconductors
1.3GHz low voltage fractional-N dual synthesizer
Product specification
SA7026
Auxiliary Output Charge Pumps
The auxiliary charge pump on pin PHA are driven by the auxiliary phase detector and PHP, PHI are driven by the main phase detector. The
current value is determined by the external resistor attached to pin RSET.
Main and auxiliary charge pump currents
CP1
CP0
IPHA
IPHP
IPHP–SU
0
0
1.5xlSET
3xISET
15xlSET
0
1
0.5xlSET
1xlSET
5xlSET
1
0
1.5xlSET
3xlSET
15xlSET
1
1
0.5xlSET
1xlSET
5xlSET
NOTES
1. ISET = VSET/RSET: bias current for charge pumps.
2. CP1 is used to disable the PHI pump, IPHP–SU is the total current at pin PHP during speed up condition.
IPHI
36xlSET
12xlSET
0
0
Lock Detect
The output LOCK maintains a logic ‘1’ when the auxiliary phase
detector ANDed with the main phase detector indicates a lock
condition. The lock condition for the main and auxiliary synthesizers
is defined as a phase difference of less than "1 period of the
frequency at the input REFin+, –. One counter can fulfill the lock
condition when the other counter is powered down. Out of lock (logic
’0’) is indicated when both counters are powered down.
Power-down mode
The power-down signal can be either hardware (PON) or software
(PD). The PON signal is exclusively ORed with the PD bits in
B-word. If PON = 0, then the part is powered up when PD = 1. PON
can be used to invert the polarity of the software bit PD. When the
synthesizer is reactivated after power-down, the main and reference
dividers are synchronized to avoid possibility of random phase
errors on power-up.
1999 Nov 04
10
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