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74F843SC

9-Bit Transparent Latch

Fairchild Semiconductor 

Unit Loading/Fan Out

Pin Names

Description

U.L.

Input IIH/IIL

HIGH/LOW Output IOH/IOL

D0–D8

OE

Data Inputs

Output Enable Input

1.0/1.0

1.0/1.0

20 µA/−0.6 mA

20 µA/−0.6 mA

LE

Latch Enable

1.0/1.0 20 µA/−0.6 mA

CLR

Clear

1.0/1.0 20 µA/−0.6 mA

PRE

Preset

1.0/1.0 20 µA/−0.6 mA

O0–O8

3-STATE Data Outputs 150/40 −3 mA/24 mA

Functional Description

The 74F843 consists of nine D-type latches with 3-STATE

outputs. The flip-flops appear transparent to the data when

Latch Enable (LE) is HIGH. This allows asynchronous

operation, as the output transition follows the data in transi-

tion. On the LE HIGH-to-LOW transition, the data that

meets the setup times is latched. Data appears on the bus

when the Output Enable (OE) is LOW. When OE is HIGH,

the bus output is in the high impedance state. In addition to

the LE and OE pins, the 74F843 has a Clear (CLR) pin and

a Preset (PRE). These pins are ideal for parity bus interfac-

ing in high performance systems. When CLR is LOW, the

outputs are LOW if OE is LOW. When CLR is HIGH, data

can be entered into the latch. When PRE is LOW, the Out-

puts are HIGH if OE is LOW. Preset overrides CLR.

Function Table

Inputs

CLR PRE OE LE

HHXX

HHHH

HHHH

HHHL

HHLH

HHLH

HHL L

HLLX

LHLX

LLLX

L HH L

HLHL

H = HIGH Voltage Level

L = LOW Voltage Level

X = Immaterial

Z = High Impedance

NC = No Change

Internal Output

Function

D

Q

O

X

X

Z

High Z

L

L

Z

High Z

H

H

Z

High Z

X NC

Z

Latched

L

L

L Transparent

H

H

H Transparent

X

NC

NC

Latched

X

H

H

Preset

X

L

L

Clear

X

H

H

Preset

X

L

Z

Latched

X

H

Z

Latched

Logic Diagram

Please note that this diagram is provided only for the understanding of logic operations and should not be used to estimate propagation delays.

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