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SAA4951

Memory controller

Philips Electronics 

Philips Semiconductors

Memory controller

Preliminary specification

SAA4951

APPLICATION INFORMATION

Fig.12 shows a block diagram of the application environment of the memory controller SAA4951. The full option chip set

of the new TV-feature system (third generation) controlled by the I2C-bus includes the following circuits:

TDA8709

TDA8755

3 × ADC (8-bit) with clamp and gain setting, 30 MHz or

1 × ADC

TMS4C10XX 1 Mbit video RAM, (optional TMS4C1050/60/70) or

TMS4C2970 2.9 Mbit video RAM

SAA7158

BENDIC (Back END IC) with LFR, CTI, Y-Peaking, DAC

SAA4940

NORIC (NOise Reduction IC) with Noise Reduction (NR) and Cross Colour Reduction (CCR)

SAA4951

Memory controller

83C652

µC software control of activated features

April 1994

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