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SAA4955TJ

2.9-Mbit field memory

Philips Electronics 

Philips Semiconductors

2.9-Mbit field memory

BLOCK DIAGRAM

Product specification

SAA4955TJ

handbook, full pagewidth

D0 to D11

12

14 to 3

IE

18

WE RSTW SWCK

17

16

15

IE internal

+3.3 V

VDD

VDD(P)

VDD(P)

VDD(O)

DATA INPUT AND

WRITE MASK

BUFFER (×13)

INPUT BUFFER 3

(×3)

SERIAL WRITE CONTROLLER

IE

internal

D0

internal

19

12 + 1

mini cache write control + cache transfer

write

control

SERIAL WRITE REGISTER

20-WORD (×13)

20 × (12 + 1)

write

load write

acknowledge block

address

CLOCK

OSCILLATOR

20

PARALLEL WRITE REGISTER

refresh clock

21

20-WORD (×13)

D0

22

20 × (12 + 1)

internal

IE

internal

100 nF

GNDP 1

GND 2

GNDO 39

GNDP 40

WRITE MINI CACHE

12-WORD (×12)

12

cache

transfer

READ MINI CACHE

12-WORD (×12)

MEMORY ARRAY

245760-WORD (×12)

MEMORY

ARBITRATION

LOGIC

WRITE ADDRESS

COUNTER

REFRESH ADDRESS

COUNTER

READ ADDRESS

COUNTER

SAA4955TJ

12

12

DATA MUX

DATA OUTPUT

BUFFER (×12)

27 to 38

12

Q0 to Q11

20 × 12

PARALLEL READ REGISTER

20-WORD (×12)

20 × 12

OE

internal

SERIAL READ REGISTER

20-WORD (×12)

mini cache read control

OE

internal INPUT BUFFER 3

(×4)

read

control

read

acknowledge

load read

block

address

SERIAL READ CONTROLLER

23 24 25 26

RE SRCK

OE RSTR

MGK676

Pins 20 and 21 (VDD(P)) should be connected to the supply voltage of the driving circuit that generates the input voltages. This could be, for instance,

5.5 V instead of 3.3 V. Pins 19 and 22 (VDD and VDD(O)) require a 3.3 V supply.

Fig.1 Block diagram.

1999 Apr 29

3

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