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SAA5361HL

Multi page intelligent teletext decoder

Philips Electronics 

Philips Semiconductors

Multi page intelligent teletext decoder

Product specification

SAA5360; SAA5361

Notes

1. Periphery current is dependent on external components and voltage levels on I/Os.

2. VTN is the drop across a protection transistor which clamps the input to VDD. The maximum value is VTN = 0.75 V

3. Crystal order number 4322 143 05561.

4. If the 4322 143 05561 crystal is not used, the formula in the crystal specification should be used. The mean of the

capacitances due to the chip at XTALIN and at XTALOUT is CIO, where CIO = 7 pF. Cext is a value for the mean of

the stray capacitances due to the external circuits at XTALIN and XTALOUT.

a) Cosc(typ) = 2CL − CIO − Cext. Capacitor Cosc may need to be reduced from the initial selected value.

b) CO(max) = 35 − 0.5 (Cosc + CIO + Cext) pF. The maximum value for the crystal holder capacitance is to ensure

start-up.

5. A device must internally provide a hold time of at least 300 ns for the SDA signal, referenced to the VIH(min) of the

SCL signal, in order to bridge the undefined region of the falling edge of SCL.

6. The maximum tHD;DAT has only to be met if the device does not stretch the LOW period of the SCL signal (tLOW(SCL)).

7. A fast mode I2C-bus device can be used in a standard-mode I2C-bus system, but the requirement tSU;DAT ≥ 250 ns

must be met. This requirement is met for a device that does not stretch tLOW(SCL). If a device does stretch tLOW(SCL),

the next data bit to the SDA line must be output tr(max) + tSU;DAT = 1000 + 250 = 1250 ns before the SCL line is

released (according to the standard-mode I2C-bus specification).

8. Cb = total capacitance of one bus line in pF.

12 APPLICATION INFORMATION

12.1 EMC guidelines

Optimization of circuit return paths and minimization of

common mode emission is achieved by a double sided

Printed-Circuit Board (PCB) with low inductance ground

plane.

On a single-sided PCB a local ground plane under the

whole IC should be present. Preferably, the PCB local

ground plane connection should not be connected to other

grounds on route to the PCB ground. Do not use wire links.

Wire links cause ground inductance which increases

ground bounce.

The supply pins can be decoupled at the ground pin plane

below the IC. This is easily achieved by using surface

mount capacitors, which, at high frequency, are more

effective than components with leads.

Using a device socket would increase the area and

therefore increase the inductance of the external bypass

loop.

To provide a high-impedance to any high frequency

signals on the VDD supplies to the IC, a ferrite bead or

inductor can be connected in series with the supply line

close to the decoupling capacitor. To prevent signal

radiation, pull-up resistors of signal outputs should not be

connected to the VDD supply on the IC side of the ferrite

bead or inductor.

OSCGND should only be connected to the crystal load

capacitors and not to any other ground connection.

Distances to physical connections of associated active

devices should be as short as possible.

PCB output tracks should have close proximity, mutually

coupled and ground return paths.

2005 Mar 09

19

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