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SAA7146A

Multimedia bridge, high performance Scaler and PCI circuit (SPCI)

Philips Electronics 

Philips Semiconductors

Multimedia bridge, high performance

Scaler and PCI circuit (SPCI)

Product specification

SAA7146A

1 FEATURES

1.1 Video processing

• Full size, full speed video delivery to and from the frame

buffer or virtual system memory enables various

processing possibilities for any external PCI device

• Full bandwidth PCI-bus master write and read (up to

132 Mbytes/s)

• Virtual memory support (4 Mbytes per DMA channel)

• Processing of maximum 4095 active samples per line

and maximum 4095 lines per frame

• Vanity picture (mirror) for video phone and video

conferencing applications

• Video flip (upside down picture)

• Colour space conversion with gamma correction for

different kinds of displays

• Chroma Key generation and utilization

• Pixel dithering for low resolution video output formats

• Brightness, contrast and saturation control

• Video and Vertical Blanking Interval (VBI) synchronized

programming of internal registers with Register

Programming Sequencer (RPS), ability to control two

asynchronous data streams simultaneously

• Memory Management Unit (MMU) supports virtual

demand paging memory management (Windows, Unix,

etc.)

• Rectangular clipping of frame buffer areas minimizes

PCI-bus load

• Random shape mask clipping protects selectable areas

of frame buffer

• 3 × 128 Dword video FIFO with overflow detection and

‘graceful’ recovery.

1.2 Audio processing

• Time Slot List (TSL) processing for flexible control of

audio frames up to 256 bits on 2 asynchronous

bidirectional digital audio interfaces simultaneously

(4 DMA channels)

• Video synchronous audio capture, e.g. for sound cards

• Various synchronization modes to support I2S-bus and

other different audio and DSP data formats

• Audio input level monitoring enables peak control via

software

• Programmable bit clock generation for master and slave

applications.

1.3 Scaling

• Scaling of video pictures down to randomly sized

windows (vertical down to 1 : 1024; horizontal down to

1 : 256)

• High Performance Scaler (HPS) offers two-dimensional,

phase correct data processing for improved signal

quality of scaled video data, especially for compression

applications

• Horizontal and vertical FIR filters with up to 65 taps

• Horizontal upscaling (zoom) supports e.g. CCIR to

square pixel conversion

• Additional Binary Ratio Scaler (BRS) supports CIF and

QCIF formats, especially for video phone and video

conferencing.

1.4 Interfacing

• Dual D1 (8-bit, CCIR 656) video I/O interface

• DMSD2 compatible (16-bit YUV) video input interface

• Supports various packed (pixel dithering) and planar

video output formats

• Data Expansion Bus Interface (DEBI) for interfacing with

e.g. MPEG or JPEG decoders with Intel (ISA like) and

Motorola (68000 like) protocol style, capability for

immediate and block mode (DMA) transfers with up to

23 Mbytes/s peak data rate

• 5 digital audio I/O ports

• 4 independent user configurable General Purpose I/O

Ports (GPI/O) for interrupt and status processing

• PCI interface (release 2.1)

• I2C-bus interface (bus master).

2004 Aug 25

3

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