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Q67101-H6788

ICs for Communications Enhanced Serial Communication Controller

Siemens AG 

SAB 82532/SAF 82532

Introduction

1.3 Pin Definitions and Functions

Pin No.

Symbol Input (I) Function

P-LCC-68 P-MQFP-80

Output (O)

2 ... 8

31 … 37

A0 ... A6 I

Address Bus

These inputs interface with seven bits of

the system’s address bus to select one of

the internal registers for read or write.

60 ... 45

19 … 4

D0 ... D15 I/O

Data Bus

Bi-directional three-state data lines which

interface with the system’s data bus. Their

configuration is controlled by the level of

pin WIDTH:

– 8-bit mode (WIDTH = 0): D0 ... D7 are

active.

D8 ... D15 are in high impedance and

have to be connected to VDD or VSS.

– 16-bit mode (WIDTH = 1): D0 ... D15

are active. In case of byte transfers, the

active half of the bus is determined by

A0 and BHE/BLE and the selected bus

interface mode (via ALE). The unused

half is in high impedance. For detailed

information, refer to chapter 3.1.

9

38

ALE

I

Address Latch Enable

The level at this pin defines the bus

interface mode:

Fixed to VSS: Demultiplexed

Siemens/Intel bus interface

Fixed to ‘1’: Demultiplexed Motorola bus

interface

Switching: Multiplexed Siemens/Intel

bus interface

The address information provided on lines

A0 ... A6 is internally latched with the

falling edge of ALE. This function allows

the ESCC2 to be directly connected to a

multiplexed address/data bus. In this

case, pins A0 ... A6 must be externally

connected to the Data Bus pins (e.g.

D0 … D6 for 8-bit CPUs).

Note: All unused input pins have to be connected to a defined level.

Semiconductor Group

11

07.96

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