SC1405BTS.TR Ver la hoja de datos (PDF) - Semtech Corporation
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SC1405BTS.TR Datasheet PDF : 13 Pages
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POWER MANAGEMENT
Block Diagram
SC1405B
Applications Information
SC1405B is the higher speed version of the SC1405.
It is designed to drive Low Rds_On power MOSFET’s with
ultra-low rise/fall times and propagation delays. As the
switching frequency of PWM controllers is increased to
reduce power supply and Class-D amplifier volume and
cost, fast rise and fall times are necessary to minimize
switching losses (TOP MOSFET) and reduce Dead-time
(BOTTOM MOSFET) losses. While Low Rds_On MOSFET’s
present a power saving in I2R losses, the MOSFET’s die
area is larger and thus the effective input capacitance
of the MOSFET is increased. Often a 50% decrease in
Rds_On more than doubles the effective input gate
charge, which must be supplied by the driver. The Rds_On
power savings can be offset by the switching and dead-
time losses with a suboptimum driver. While discrete
solution can achieve reasonable drive capability, imple-
menting shoot-through, programmable delay and other
housekeeping functions necessary for safe operation can
become cumbersome and costly. The SC1405 family of
parts presents a total solution for the high-speed, high
power density =applications. Wide input supply range of
4.5V-25V allows use in battery powered applications, new
high voltage, distributed power servers as well as Class-
D amplifiers.
of events by which the top and bottom drive signals are
applied. The shoot-through protection is implemented
by holding the bottom FET off until the voltage at the
phase node (intersection of top FET source, the output
inductor and the bottom FET drain) has dropped below
1V. This assures that the top FET has turned off and
that a direct current path does not exist between the
input supply and ground, a condition which both the top
and bottom FET’s are on momentarily. The top FET is
also prevented from turning on until the bottom FET is
off. This time is internally set to 20ns (typical) and may
be increased by adding a capacitor from the C-Delay pin
to GND. The delay is approximately 1ns/pf in addition to
the internal 20ns delay. The external capacitor may be
needed if multiple High input capacitance MOSFET’s are
used in parallel and the fall time is substantially greater
than 20ns.
It must be noted that increasing the dead-time by high
values of C-Delay capacitor will reduce efficiency since
the parallel Schottky or the bottom FET body diode will
have to conduct during dead-time.
Layout Guidelines
Theory of Operation
The control input (CO) to the SC1405B is typically sup-
plied by a PWM controller that regulates the power sup-
ply output. (See Application Evaluation Schematic, Fig-
ure 3). The timing diagram demonstrates the sequence
As with any high speed , high current circuit, proper lay-
out is critical in achieving optimum performance of the
SC1405B. The Evaluation board schematic (Refer to
figure 3) shows a dual phase synchronous design with all
surface mountable components.
2004 Semtech Corp.
7
www.semtech.com
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