SC4603(2004) Ver la hoja de datos (PDF) - Semtech Corporation
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SC4603 Datasheet PDF : 16 Pages
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SC4603
POWER MANAGEMENT
Applications Information - (Cont.)
Where
1
ωI = R7 ⋅ (C1 + C2 )
1
ωZ1 = R1 ⋅ C2
1
ωZ2 = (R7 + R8 ) ⋅ C9
ωP1
=
C1 + C2
R1 ⋅ C1 ⋅ C2
1
ωP2 = R8 ⋅ C9
After the compensation, the converter will have the
following loop gain:
T(s) = GPWM ⋅ GCOMP (s) ⋅ GVD (s) =
1
VM
⋅ ωI ⋅ VIN
s
1+
⋅
1+
s
ωZ1
s
ωP1
1+ s
⋅
⋅
1
+
ωZ2
s
ωP2
1+
s
1
⋅
1
+
s
RC ⋅ C4
L
R
+
s2LC
Where:
GPWM = PWM gain and
VM = 1.0V, ramp peak to valley voltage of SC4603.
The design guidelines for the SC4603 applications are
as following:
1. Set the loop gain crossover corner frequency
ωC for given switching corner frequency
ωS =2 πfs,
2. Place an integrator at the origin to increase DC
and low frequency gains.
3. Select ωZ1 and ωZ2 such that they are placed
near ωO to damp the peaking and the loop gain
has a -20dB/dec rate to go across the 0dB
line for obtaining a wide bandwidth.
4. Cancel the zero from C4’s ESR by a compensa-
tor pole ωP1 (ωP1 = ωESR = 1/( RCC4)),
5. Place a high frequency compensator pole ωp2
(ωp2 = πpfs) to get the maximum attenuation of
the switching ripple and high frequency noise
with the adequate phase lag at ωC.
The compensated loop gain will be as given in Figure 4:
T
ωZ1
ωo
Loop gain T(s)
ωZ2
-20dB/dec
Gd
ωc
0dB
ωp1
ω p2
Power stage GVD(s)
-40dB/dec
ω ESR
Figure 4. Asymptotic diagrams of power stage and its
loop gain.
Layout Guidelines
In order to achieve optimal electrical, thermal and noise
performance for high frequency converters, special at-
tention must be paid to the PCB layouts. The goal of lay-
out optimization is to identify the high di/dt loops and
minimize them. The following guideline should be used to
ensure proper functions of the converters.
1. A ground plane is recommended to minimize noises
and copper losses, and maximize heat dissipation.
2. Start the PCB layout by placing the power compo-
nents first. Arrange the power circuit to achieve a
clean power flow route. Put all the connections on
one side of the PCB with wide copper filled areas if
possible.
3. The VCC bypass capacitor should be placed next to
the VCC and GND pins.
4. The trace connecting the feedback resistors to the
output should be short, direct and far away from the
noise sources such as switching node and switching
components.
5. Minimize the traces between PDRV/NDRV and the
gates of the MOSFETs to reduce their impedance to
drive the MOSFETs.
6. Minimize the loop including input capacitors, top/bot-
tom MOSFETs. This loop passes high di/dt current.
Make sure the trace width is wide enough to reduce
copper losses in this loop.
7. ISET and PHASE connections to P-MOSFET for cur-
rent sensing must use Kelvin connections.
2004 Semtech Corp.
12
www.semtech.com
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