SC4605 Ver la hoja de datos (PDF) - Semtech Corporation
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SC4605 Datasheet PDF : 19 Pages
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SC4605
POWER MANAGEMENT
Applications Information (Cont.)
Layout Guideline
The design guidelines for the SC4605 applications are
as following:
1. Set the loop gain crossover corner frequency ωC for
given switching corner frequency ωS =2πfs,
2. Place an integrator at the origin to increase DC and
low frequency gains,
3. Select ωZ1 and ωZ2 such that they are placed near
ωO to damp the peaking and the loop gain has a
-20dB/dec rate to go across the 0dB line for
obtaining a wide bandwidth,
4. Cancel the zero from C ’s ESR by a compensator
4
pole
ωP1 ( ωP1 =
ωESR
=
1/(
R C )),
C4
5. Place a high frequency compensator pole
ωp2 ( ωp2 = πfs) to get the maximum attenuation of
the switching
ripple and high frequency noise with the adequate
phase lag at ωC.
The compensated loop gain will be as given in Figure 4:
T
ωZ1
ωo
Loop gain T(s)
ωZ2
-20dB/dec
Gvd
ωc
0dB
ωp1
ω p2
Power stage GVD(s)
-40dB/dec
ω ESR
In order to achieve optimal electrical, thermal and noise
performance for high frequency converters, special at-
tention must be paid to the PCB layouts. The goal of lay-
out optimization is to identify the high di/dt loops and
minimize them. The following guideline should be used to
ensure proper functions of the converters.
1. A ground plane is recommended to minimize noises
and copper losses, and maximize heat dissipation.
2. Start the PCB layout by placing the power compo-
nents first. Arrange the power circuit to achieve a
clean power flow route. Put all the connections on
one side of the PCB with wide copper filled areas if
possible.
3. The Vcc bypass capacitor should be placed next to
the Vcc and GND pins.
4. The trace connecting the feedback resistors to the
output should be short, direct and far away from the
noise sources such as switching node and switching
components.
5. Minimize the traces between DRVH/DRVL and the
gates of the MOSFETs to reduce their impedance to
drive the MOSFETs.
6. Minimize the loop including input capacitors, top/bot-
tom MOSFETs. This loop passes high di/dt current.
Make sure the trace width is wide enough to reduce
copper losses in this loop.
7. ISET and PHASE connections to the top MOSFET for
current sensing must use Kelvin connections.
8. Maximize the trace width of the loop connecting the
inductor, bottom MOSFET and the output capacitors.
9. Connect the ground of the feedback divider and the
compensation components directly to the GND pin
of the SC4605 by using a separate ground trace.
Then connect this pin to the ground of the output
capacitor as close as possible.
Figure 4. Asymptotic diagrams of power stage and its
loop gain
2004 Semtech Corp.
11
www.semtech.com
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