CD1283 Ver la hoja de datos (PDF) - Intel

Número de pieza

componentes Descripción

Lista de partido

CD1283

IEEE 1284-Compatible Parallel Interface

Intel 

IEEE 1284-Compatible Parallel Interface — CD1283

Contents

1.0

Overview ........................................................................................................................ 9

1.1 Advantages ........................................................................................................... 9

2.0

Conventions ...............................................................................................................11

3.0

Pin Information..........................................................................................................13

3.1 Pin Diagram.........................................................................................................13

3.2 Pin List.................................................................................................................14

3.3 Pin Descriptions ..................................................................................................16

4.0

Register Summary ...................................................................................................19

4.1 Register Summary Tables...................................................................................19

5.0

Functional Description...........................................................................................22

5.1 Device Architecture .............................................................................................22

5.2 CPU Interface......................................................................................................22

5.2.1 Read Cycles ...........................................................................................24

5.2.2 Write Cycles ...........................................................................................24

5.2.3 Service-Acknowledge Cycles .................................................................24

5.2.4 DMA Cycles............................................................................................24

5.2.5 Interrupts ................................................................................................25

5.2.6 DMAREQ* as Interrupt Source...............................................................25

5.2.7 Daisy-Chain Configurations....................................................................26

5.3 Parallel Port Service Requests............................................................................27

5.3.1 Hardware-Activated Acknowledge .........................................................32

5.3.2 Software-Activated Acknowledge...........................................................32

5.4 Parallel Port FIFO and Data Pipeline ..................................................................32

5.4.1 IEEE Standard 1284 Protocols...............................................................33

5.4.2 Bus Interface ..........................................................................................33

5.4.3 Parallel Port FIFO...................................................................................34

5.4.4 Receive Direction ...................................................................................34

5.4.5 Receiving Compressed Data..................................................................35

5.4.6 Stale Data (Stale, OneChar, and Timeout Status Bits) ..........................35

5.4.7 Transmit Direction ..................................................................................36

5.5 Parallel Port Overview.........................................................................................36

5.5.1 Terminology............................................................................................36

5.5.2 Signal Names .........................................................................................37

5.5.3 State Machine ........................................................................................37

5.5.4 Configuration ..........................................................................................37

5.5.5 Interrupts ................................................................................................37

5.5.6 Manual Mode..........................................................................................38

5.5.7 Control Signals .......................................................................................38

5.5.8 Parallel Port Interface to the FIFO..........................................................39

5.5.9 IEEE 1284-Protocol Negotiations...........................................................39

5.5.10 Data Transfers........................................................................................40

5.5.11 Compatibility Mode Status......................................................................40

5.6 IEEE 1284 Parallel Protocol Support ..................................................................40

Datasheet

3

Share Link: