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SCN2652

Multi-protocol communications controller(MPCC)

Philips Electronics 

Philips Semiconductors

Multi-protocol communications controller (MPCC)

Product specification

SCN2652/SCN68652

TIMING DIAGRAMS (Continued)

TxC

TxSO

CLOCK

1/f

tCLK1

tCLK0

TxD

RxC

RxSI

tCLK0

tRxS

tCLK1

tRxH

TxC

TxSO

3

TxBE

SET TSOM

DBEN

MARK

Figure 11. Timing Diagrams (cont.)

TRANSMIT – START OF MESSAGE

8 TxC1

SYNC/FLAG1

LOAD 1st CHAR RESET TSOM

SD00066

1ST CHAR

LOAD 2nd CHAR

TxE

2

TxA

NOTES:

1. SYNC may be 5 to 8 bits and will contain parity bit as specified.

2. TxA goes high relative to TxC rising edge after TSOM has been set and TxE has been raised.

3. TxBE goes low relative to DBEN falling edge on the first write transfer into TDSR. It is reasserted 1 TxC time before the first bit of the transmitted SYNC/FLAG. TxBE then goes

low relative to DBEN falling edge when writing into TDSRH and/or TDSRL. It is reasserted on the rising edge of the TxC that corresponds to the transmission of the last bit of each

character, except in BOP mode when the CRC is to be sent as the next character (see Transmit Timing–End of Message).

SD00067

Figure 12. Timing Diagrams (cont.)

1995 May 01

18

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