SCN2681 Ver la hoja de datos (PDF) - Philips Electronics

Número de pieza

componentes Descripción

Lista de partido

SCN2681

Dual asynchronous receiver/transmitter (DUART)

Philips Electronics 

Philips Semiconductors

Dual asynchronous receiver/transmitter (DUART)

Product specification

SCN2681

(IMR) and the Interrupt Status Register (ISR). The IMR may be

programmed to select only certain conditions to cause INTRN to be

asserted. The ISR can be read by the CPU to determine all

currently active interrupting conditions.

Outputs OP3-OP7 can be programmed to provide discrete interrupt

outputs for the transmitter, receivers, and counter/timer.

Timing Circuits

The timing block consists of a crystal oscillator, a baud rate

generator, a programmable 16-bit counter/timer, and four clock

selectors. The crystal oscillator operates directly from a 3.6864MHz

crystal connected across the X1/CLK and X2 inputs. If an external

clock of the appropriate frequency is available, it may be connected

to X1/CLK. The clock serves as the basic timing reference for the

Baud Rate Generator (BRG), the counter/timer, and other internal

circuits. A clock signal within the limits specified in the

specifications section of this data sheet must always be supplied to

the DUART.

If an external clock is used instead of a crystal, both X1 and X2

should use a configuration similar to the one in Figure 7.

The baud rate generator operates from the oscillator or external

clock input and is capable of generating 18 commonly used data

communications baud rates ranging from 50 to 38.4k baud. The

clock outputs from the BRG are at 16X the actual baud rate. The

counter/timer can be used as a timer to produce a 16X clock for any

other baud rate by counting down the crystal clock or an external

clock. The four clock selectors allow the independent selection, for

each receiver and transmitter, of any of these baud rates or external

timing signal.

Counter/Timer (C/T)

The counter timer is a 16 bit programmable divider that operates

one of three modes: Counter, Timer or Time Out mode. In all three

modes it uses the 16-bit value loaded to the CTUR and CTLR

registers. (Counter timer upper and lower preset registers).

• In the timer mode it generates a square wave.

• In the counter mode it generates a time delay.

• In the time out mode it monitors the receiver data flow and signals

data flow has paused. In the time out mode the receiver controls

the starting/stopping of the C/T.

The counter operates as a down counter and sets its output bit in

the ISR (Interrupt Status Register) each time it passes through 0.

The output of the counter/timer may be seen on one of the OP pins

or as an Rx or Tx clock.

The Timer/Counter is controlled with six (6) “commands”; Start C/T,

Stop C/T, write C/T, preset registers, read C/T value, set or reset

time out mode.

Please see the detail of the commands under the Counter/Timer

register descriptions.

Communications Channels A and B

Each communications channel of the SCN2681 comprises a

full-duplex asynchronous receiver/transmitter (UART). The

operating frequency for each receiver and transmitter can be

selected independently from the baud rate generator, the counter

timer, or from an external input.

The transmitter accepts parallel data from the CPU, converts it to a

serial bit stream, inserts the appropriate start, stop, and optional

parity bits and outputs a composite serial stream of data on the TxD

output pin. The receiver accepts serial data on the RxD pin,

converts this serial input to parallel format, checks for start bit, stop

bit, parity bit (if any), or break condition and sends an assembled

character to the CPU.

The input port pulse detection circuitry uses a 38.4kHz sampling

clock derived from one of the baud rate generator taps. This results

in a sampling period of slightly more than 25µs (this assumes that

the clock input is 3.6864MHz). The detection circuitry, in order to

guarantee that a true change in level has occurred, requires two

successive samples at the new logic level be observed. As a

consequence, the minimum duration of the signal change is 25µs if

the transition occurs “coincident with the first sample pulse”. The

50µs time refers to the situation in which the change-of-state is “just

missed” and the first change-of-state is not detected until 25µs later.

Input Port

The inputs to this unlatched 7-bit port can be read by the CPU by

performing a read operation at address D16. A High input results in

a logic 1 while a Low input results in a logic 0. D7 will always read

as a logic 1. The pins of this port can also serve as auxiliary inputs

to certain portions of the DUART logic.

Four change-of-state detectors are provided which are associated

with inputs IP3, IP2, IP1 and IP0. A High-to-Low or Low-to-High

transition of these inputs lasting longer than 25 – 50µs, will set the

corresponding bit in the input port change register. The bits are

cleared when the register is read by the CPU. Any change-of-state

can also be programmed to generate an interrupt to the CPU.

All the IP pins have a small pull-up device that will source 1 to 4 mA

of current from VCC. These pins do not require pull-up devices or

VCC connections if they are not used.

Output Port

The output port pins may be controlled by the OPR, OPCR, MR and

CR registers. Via appropriate programming they may be just

another parallel port to external circuits, or they may represent many

internal conditions of the UART. When this 8-bit port is used as a

general purpose output port, the output port pins drive a state which

is the complement of the Output Port Register (OPR). OPR(n) = 1

results in OP(n) = Low and vice versa. Bits of the OPR can be

individually set and reset. A bit is set by performing a write operation

at address E16 with the accompanying data specifying the bits to be

set (1 = set, 0 = no change).

Likewise, a bit is reset by a write at address F16 with the

accompanying data specifying the bits to be reset (1 = reset, 0 = no

change).

Outputs can be also individually assigned specific functions by

appropriate programming of the Channel A mode registers (MR1A,

MR2A), the Channel B mode registers (MR1B, MR2B), and the

Output Port Configuration Register (OPCR).

Please note that these pins drive both high and low. HOWEVER

when they are programmed to represent interrupt type functions

(such as receiver ready, transmitter ready or counter/timer ready)

they will be switched to an open drain configuration in which case an

external pull-up device would be required.

TRANSMITTER OPERATION

The SCN2681 is conditioned to transmit data when the transmitter is

enabled through the command register. The SCN2681 indicates to

the CPU that it is ready to accept a character by setting the TxRDY

bit in the status register. This condition can be programmed to

1998 Sep 04

8

Share Link: