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SCN2681T

Dual asynchronous receiver/transmitter (DUART)

Philips Electronics 

Philips Semiconductors

Dual asynchronous receiver/transmitter (DUART)

Product specification

SCN2681T

RDN

tPS

IP0–IP6

WRN

OP0–OP7

tPH

(a) INPUT PINS

tPD

OLD DATA

(b) OUTPUT PINS

Figure 5. Port Timing

NEW DATA

SD00101

SYMBOL

PARAMETER1

LIMITS

Min

Max

UNIT

tPS

Port input setup time before RDN low

tPH

Port input hold time after RDN high

tPD

Port output valid after WRN high

0

ns

0

ns

200

ns

NOTE:

1. For bus operations, CEN and RDN (also CEN and WRN) are ANDed internally. As a consequence, the signal asserted last initiates the cycle

and the signal negated first terminates the cycle.

WRN

VM

INTERRUPT1

OUTPUT

tIR

VOL +0.5V

VOL

NOTES:

1. INTRN or OP3-OP7 when used as interrupt outputs.

2. The test for open drain outputs is intended to guarantee switching of the output transistor. Measurement of this response is referenced from the midpoint of the switching

signal, VM, to a point 0.5V above VOL. This point represents noise margin that assures true switching has occurred. Beyond this level, the effects of external circuitry and

test environment are pronounced and can greatly affect the resultant measurement.

SD00102

Figure 6. Interrupt Timing

SYMBOL

tIR

PARAMETER

INTRN (or OP3–OP7 when used as interrupts) negated from:

Read RHR (RxRDY/FFULL interrupt)

Write THR (TxRDY interrupt)

Reset command (delta break interrupt)

Stop C/T command (counter interrupt)

Read IPCR (input port change interrupt)

Write IMR (clear of interrupt mask bit)

LIMITS

Min

Max

200

200

200

200

200

200

UNIT

ns

ns

ns

ns

ns

ns

1998 Sep 04

8

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