SED1335 Ver la hoja de datos (PDF) - Unspecified
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SED1335 Datasheet PDF : 14 Pages
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° Display Memory Write Timing
SED1335
EXTφ0
VCE
VA0 to VA15
VRW
VD0 to VD7
tC
tW
tASC
tWSC
tAS
tDSC
tCE
tCYW
tAHC
tWHC
tDHC
tCA
tAH2
tDH2
Signal
EXT φ0
VCE
VA0 to
VA15
VWR
VD0 to
VD7
Symbol
tC
tW
tCE
tCYW
tAHC
tASC
tCA
tAS
tAH2
tWSC
tWHC
tDSC
tDHC
tDH2
Parameter
VDD = 4.5 to 5.5V
min
max
Clock period
100
—
VCE HIGH-level pulse-
width
tC – 50
—
VCE LOW-level pulse-
width
2tC – 30
—
Write cycle time
3tC
—
Address hold time from
falling edge of VCE
2tC – 30
—
Address setup time to
falling edge of VCE
tC – 70
—
Address hold time from
rising edge of VCE
0
—
Address setup time to
falling edge of VWR
0
—
Address hold time from
rising edge of VWR
10
—
Write setup time to
falling edge of VCE
tC – 80
—
Write hold time from
falling edge of VCE
2tC – 20
—
Data input setup time
to falling edge of VCE
tC – 85
—
Data input hold time
from falling edge of VCE
2tC – 30
—
Data hold time from
rising edge of VWR
5
50
VDD = 2.7 to 4.5V
min
max
125
—
tC – 50
—
2tC – 30 —
3tC
—
2tC – 40 —
tC – 110 —
0
—
0
—
10
—
tC – 115 —
2tC – 20 —
tC – 125 —
2tC – 30 —
5
50
Ta = –20 to 75°C
Unit Condition
ns
ns
ns
ns
ns
ns
ns
CL =
ns
100 pF
ns
ns
ns
ns
ns
ns
Note: VD0 to VD7 are latching input/outputs. While the bus is high impedance, VD0 to VD7 retain the write data until the data read
from the memory is placed on the bus.
147
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