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SH-2A

Renesas 32-Bit RISC Microcomputer SuperH™ RISC engine Family

Renesas Electronics 

Item

4.3 Instruction

Format

Table 4.8

Instruction Formats

Page

45

Revision (See Manual for Details)

Table amended

Instruction Formats

nid format

32

xxxx nnnn x i i i

16

xxxx

15

0

xxxx dddd dddd dddd

5.1 Instruction Set 53

by Classification

Table 5.2

Instruction Code

Format

5.1.1 Data Transfer 56

Instructions

Table 5.3 Data

Transfer Instructions

6.2 Format of

76

Instruction

Descriptions

6.3.30 RESBANK 145

REStore from

registerBANK

System Control

Instruction

6.4.21 DT

196

Decrement and Test

Arithmetic Instruction

6.4.31 MOV

219

MOVe immediate

data

Data Transfer

Instruction

Table amended

Item

Instruction

Format

Explanation

Rm:

Rn:

imm:

disp:

Source register

Destination register

Immediate data

Displacement*1

Table amended

MOVML.L @R15+,Rn

MOVMU.L @R15+,Rn

Note: When Rn = R15, read Rn as PR

Description amended

Register bank structure definition

(VTO: Interrupt vector table address offset)

Note amended

* 19 when a bank overflow has occurred and the register is

restored from the stack

Program listing amended

DT R5

Description amended

⋅⋅⋅ The PC points to the starting address of the fourth byte after this

MOV instruction. ⋅⋅⋅ The PC points to the starting address of the

fourth byte after this MOV instruction,⋅⋅⋅

Rev. 3.00 Jul 08, 2005 page iv of xiv

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