SH7011 Ver la hoja de datos (PDF) - Renesas Electronics
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SH7011 Datasheet PDF : 292 Pages
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6.4.2 Stack after Interrupt Exception Processing .......................................................... 70
6.5 Interrupt Response Time.................................................................................................... 70
Section 7 Bus State Controller (BSC) ......................................................................... 73
7.1 Overview............................................................................................................................ 73
7.1.1 Features ................................................................................................................ 73
7.1.2 Block Diagram...................................................................................................... 74
7.1.3 Pin Configuration ................................................................................................. 75
7.1.4 Register Configuration ......................................................................................... 75
7.1.5 Address Map ........................................................................................................ 76
7.2 Description of Registers .................................................................................................... 77
7.2.1 Bus Control Register 2 (BCR2)............................................................................ 77
7.2.2 Wait Control Register 1 (WCR1) ......................................................................... 80
7.3 Accessing Ordinary Space................................................................................................. 82
7.3.1 Basic Timing ........................................................................................................ 82
7.3.2 Wait State Control................................................................................................ 83
7.3.3 CS Assert Period Extension.................................................................................. 85
7.4 Waits between Access Cycles ........................................................................................... 86
7.4.1 Prevention of Data Bus Conflicts ......................................................................... 86
7.4.2 Simplification of Bus Cycle Start Detection ........................................................ 87
7.5 Memory Connection Examples ......................................................................................... 88
Section 8 Multifunction Timer Pulse Unit (MTU).................................................. 89
8.1 Overview............................................................................................................................ 89
8.1.1 Features ................................................................................................................ 89
8.1.2 Block Diagram...................................................................................................... 92
8.1.3 Pin Configuration ................................................................................................. 93
8.1.4 Register Configuration ......................................................................................... 94
8.2 MTU Register Descriptions............................................................................................... 95
8.2.1 Timer Control Register (TCR) ............................................................................. 95
8.2.2 Timer Mode Register (TMDR) ............................................................................ 99
8.2.3 Timer I/O Control Register (TIOR) ..................................................................... 100
8.2.4 Timer Interrupt Enable Register (TIER) .............................................................. 107
8.2.5 Timer Status Register (TSR) ................................................................................ 109
8.2.6 Timer Counters (TCNT)....................................................................................... 111
8.2.7 Timer General Register (TGR) ............................................................................ 112
8.2.8 Timer Start Register (TSTR)................................................................................ 112
8.2.9 Timer Synchro Register (TSYR).......................................................................... 113
8.3 Bus Master Interface.......................................................................................................... 114
8.3.1 16-Bit Registers.................................................................................................... 114
8.3.2 8-Bit Registers...................................................................................................... 114
8.4 Operation ........................................................................................................................... 116
8.4.1 Overview .............................................................................................................. 116
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