UPD16334 Ver la hoja de datos (PDF) - NEC => Renesas Technology

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UPD16334

96-Bit AC-PDP DRIVER

NEC => Renesas Technology 

µPD16334

PIN DESCRIPTION

Symbol

Pin Name

Description

PC

Polarity change input

PC = L: All driver output invert

BLK

Blank input

BLK = H : All output = H or L

LE

Latch enable input

Automatically executes latch by setting high at rising edge

of the clock

OE

Output enable

Make output high impedance by input H

A1 to A3 (6)

RIGHT data input/output (Note)

When R/L=H (values in parentheses are for 6-bit input)

B1 to B3 (6)

LEFT data input/output (Note)

A1 to A3 (6) : Input B1 to B3 (6) : Output

When R/L=L (values in parentheses are for 6-bit input)

A1 to A3 (6) : Output B1 to B3 (6) : Input

CLK

Clock input

Shift executed on fall

R/L

Shift control input

Right shift mode when R/L= H

SR1 : A1 → S1...S94 → B1 (Same direction for SR2 to SR6)

Left shift mode when R/L= L

SR1 : B1 → S94...S1 → A1 (Same direction for SR2 to SR6)

IBS

Input mode switch

H: 32-bit length shift register, 3-bit input

L: 16-bit length shift register, 6-bit input

O1 to O96

VDD1

High withstand voltage output

Power supply for logic block

80 V, 50 mAMAX.

5 V ± 10 %

VDD2

Power supply for driver block

10 to 70 V

VSS1

Logic GND

Connect to system GND

VSS2

Driver GND

Connect to system GND

Note When input mode is 3-bit, set unused input and output pins “L” level.

TRUTH TABLE 1 (Shift Register Block)

Input

R/L

CLK

H

↓

H

H or L

L

↓

L

H or L

Output

A

B

Input

Output Note1

Output

Output Note2 Input

Output

Shift Register

Right shift execution

Hold

Left shift execution

Hold

Notes 1. The data of S91 to S93 (S85 to S90) shifts to S94 to S96 (S91 to S96) and is output from B1 to B3 (B1 to B6) at the falling

edge of the clock, respectively. (Values in parentheses are for 6-bit input)

2. The data of S4 to S6 (S7 to S12) shifts to S1 to S3 (S1 to S6) and is output from A1 to A3 (A1 to A6) at the falling

edge of the clock, respectively (Values in parentheses are for 6-bit input)

TRUTH TABLE 2 (Latch Block)

LE

CLK

Output State of Latch Block (Ln)

H

↑

Latch Sn data and hold output data

↓

Hold latch data

L

X

Hold latch data

TRUTH TABLE 3 (Driver Block)

Ln

BLK

PC

X

H

H

X

H

L

X

L

H

X

L

L

X

X

X

X: H or L, H: High level, L: Low level

4

OE

Output State of Driver Block

L

H (All driver outputs: H)

L

L (All driver outputs: L)

L

Output latch data (Ln)

L

Output inverted latch data (Ln)

H

Set output impedance high

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