datasheetbank_Logo
búsqueda de Hoja de datos y gratuito Fichas de descarga

CS8427-IZ Ver la hoja de datos (PDF) - Cirrus Logic

Número de pieza
componentes Descripción
Lista de partido
CS8427-IZ Datasheet PDF : 59 Pages
1 2 3 4 5 6 7 8 9 10 Next Last
CS8427
11.14 Receiver Error (10h) (Read Only)................................................................................. 35
11.15 Receiver Error Mask (11h) ........................................................................................... 36
11.16 Channel Status Data Buffer Control (12h).................................................................... 36
11.17 User Data Buffer Control (13h) ..................................................................................... 37
11.18 Q-Channel Subcode Bytes 0 to 9 (14h - 1Dh) (Read Only) ......................................... 37
11.19 OMCK/RMCK Ratio (1Eh) (Read Only)........................................................................ 38
11.20 C-bit or U-bit Data Buffer (20h - 37h) ........................................................................... 38
11.21 CS8427 I.D. and Version Register (7Fh) (Read Only) ................................................. 38
12. PIN DESCRIPTION - SOFTWARE MODE ........................................................................... 39
13. HARDWARE MODE DESCRIPTION ................................................................................... 42
13.1 Serial Audio Port Formats ............................................................................................. 42
14. PIN DESCRIPTION - HARDWARE MODE .......................................................................... 44
15. APPLICATIONS ................................................................................................................... 46
15.1 Reset, Power Down and Start-up .................................................................................. 46
15.2 ID Code and Revision Code .......................................................................................... 46
15.3 Power Supply, Grounding, and PCB layout ................................................................... 46
15.4 Synchronization of Multiple CS8427s ............................................................................ 46
16. PACKAGE DIMENSIONS .................................................................................................... 47
17. APPENDIX A: EXTERNAL AES3/SPDIF/IEC60958 TRANSMITTER AND RECEIVER COMPO-
NENTS .................................................................................................................................. 49
17.1 AES3 Transmitter External Components ....................................................................... 49
17.2 Isolating Transformer Requirements ............................................................................. 49
17.3 AES3 Receiver External Components ........................................................................... 50
17.4 Isolating Transformer Requirements ............................................................................. 50
18. APPENDIX B: CHANNEL STATUS AND USER DATA BUFFER MANAGEMENT ........... 51
18.1 AES3 Channel Status(C) Bit Management .................................................................... 51
18.1.1 Manually accessing the E buffer ....................................................................... 51
18.1.2 Reserving the first 5 bytes in the E buffer ......................................................... 52
18.1.3 Serial Copy Management System (SCMS) ....................................................... 52
18.1.4 Channel Status Data E Buffer Access .............................................................. 52
18.2 AES3 User (U) Bit Management .................................................................................... 53
18.2.1 Mode 1: Transmit All Zeros ............................................................................... 53
18.2.2 Mode 2: Block Mode ......................................................................................... 53
19. APPENDIX C: PLL FILTER .................................................................................................. 54
19.1 General .......................................................................................................................... 54
19.2 External Filter Components ........................................................................................... 55
19.2.1 General ............................................................................................................. 55
19.2.2 Capacitor Selection ........................................................................................... 55
19.2.3 Circuit Board Layout ......................................................................................... 55
19.3 Component Value Selection .......................................................................................... 56
19.3.1 Identifying the Part Revision ............................................................................. 56
19.3.2 Locking to the RXP/RXN Receiver Inputs ......................................................... 56
19.3.3 Locking to the ILRCK Input ............................................................................... 57
19.3.4 Jitter Tolerance ................................................................................................. 57
19.3.5 Jitter Attenuation ............................................................................................... 58
20. REVISION HISTORY ............................................................................................................ 59
LIST OF FIGURES
Figure 1. Audio Port Master Mode Timing ...................................................................................... 8
Figure 2. Audio Port Slave Mode and Data Input Timing................................................................ 8
Figure 3. SPI Mode timing............................................................................................................... 9
Figure 4. I²C Mode timing.............................................................................................................. 10
Figure 5. Recommended Connection Diagram for Software Mode .............................................. 11
DS477F1
3

Share Link: 

datasheetbank.com [ Privacy Policy ] [ Request Datasheet ] [ Contact Us ]