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CS8405A
(Rev.:2002)

96 kHz Digital Audio Interface Transmitter

Cirrus Logic 

CS8405A

3. GENERAL DESCRIPTION

The CS8405A is a monolithic CMOS device which

encodes and transmits audio data according to the

AES3, IEC60958, S/PDIF, and EIAJ CP1201 inter-

face standards. The CS8405A accepts audio, chan-

nel status and user data, which is then multiplexed,

encoded, and driven onto a cable.

The audio data is input through a configurable, 3-

wire input port. The channel status bits and user bit

data are input through an SPI or Two-Wire Mode

microcontroller port and may be assembled in sep-

arate block sized buffers.

For systems with no microcontroller, a stand alone

mode allows direct access to channel status and

user data input pins.

Target applications include CD-R, DAT, DVD,

MD and VTR equipment, mixing consoles, digital

audio transmission equipment, high quality A/D

converters, effects processors, set-top TV boxes,

and computer audio systems.

Figure 5 shows the supply and external connec-

tions to the CS8405A when configured for opera-

tion with a microcontroller.

3.1 AES3 and S/PDIF Standards

Documents

This data sheet assumes that the user is familiar

with the AES3 and S/PDIF data formats. It is advis-

able to have current copies of the AES3 and

IEC60958 specifications on hand for easy refer-

ence.

The latest AES3 standard is available from the Au-

dio Engineering Society or ANSI at www.aes.org

or www.ansi.org. Obtain the latest IEC60958 stan-

dard from ANSI or from the International Electro-

technical Commission at www.iec.ch. The latest

EIAJ CP-1201 standard is available from the Japa-

nese Electronics Bureau.

Crystal Application Note 22: Overview of Digital

Audio Interface Data Structures contains a useful

tutorial on digital audio specifications, but it should

not be considered a substitute for the standards.

The paper An Understanding and Implementation

of the SCMS Serial Copy Management System for

Digital Audio Transmission, by Clifton Sanchez, is

an excellent tutorial on SCMS. It is available from

the AES as preprint 3518.

4. THREE-WIRE SERIAL INPUT AUDIO

PORT

A 3-wire serial audio input port is provided. The in-

terface format can be adjusted to suit the attached

device through the control registers. The following

parameters are adjustable:

• Master or slave

• Serial clock frequency

• Audio data resolution

• Left or right justification of the data relative to

left/right clock

• Optional one-bit cell delay of the first data bit

• Polarity of the bit clock

• Polarity of the left/right clock. (By setting the

appropriate control bits, many formats are pos-

sible).

Figure 6 shows a selection of common input for-

mats with the corresponding control bit settings.

In master mode, the left/right clock and the serial

bit clock are outputs, derived from the OMCK in-

put pin master clock.

In slave mode, the left/right clock and the serial bit

clock are inputs. The left/right clock must be syn-

chronous to the OMCK master clock, but the serial

bit clock can be asynchronous and discontinuous if

required. The left/right clock should be continuous,

but the duty cycle can be less than the specified typ-

ical value of 50% if enough serial clocks are

present in each phase to clock all the data bits.

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DS469PP4

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