CS8405A(2002) Ver la hoja de datos (PDF) - Cirrus Logic
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CS8405A Datasheet PDF : 36 Pages
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CS8405A
8.4 Clock Source Control (4h)
7
6
5
4
3
2
1
0
0
RUN
CLK1
CLK0
0
0
0
0
This register configures the clock sources of various blocks. In conjunction with the Data Flow Control register, var-
ious Receiver/Transmitter/Transceiver modes may be selected.
RUN - Controls the internal clocks, allowing the CS8405A to be placed in a “powered down” low
current consumption, state.
Default = ‘0’
0 - Internal clocks are stopped. Internal state machines are reset. The fully static
control port registers are operational, allowing registers to be read or changed. Reading and
writing the U and C data buffers is not possible. Power consumption is low.
1 - Normal part operation. This bit must be set to 1 to allow the CS8405A
to begin operation. All input clocks should be stable in frequency and phase when
RUN is set to 1.
CLK1:0 - Output master clock (OMCK) input frequency to output sample rate (Fs) ratio selector.
If these bits are changed during normal operation, then always stop the CS8405A first (RUN = 0),
write the new value, then start the CS8405A (RUN = 1).
Default = ‘00’
00 - OMCK frequency is 256*Fs
01 - OMCK frequency is 384*Fs
10 - OMCK frequency is 512*Fs
11 - Reserved
8.5 Serial Audio Input Port Data Format (5h)
7
SIMS
6
SISF
5
SIRES1
4
SIRES0
3
SIJUST
2
SIDEL
1
SISPOL
0
SILRPOL
SIMS - Master/Slave Mode Selector
Default = ‘0’
0 - Serial audio input port is in slave mode
1 - Serial audio input port is in master mode
SISF - ISCLK frequency (for master mode)
Default = ‘0’
0 - 64*Fs
1 - 128*Fs
SIRES1:0 - Resolution of the input data, for right-justified formats
Default = ‘00’
00 - 24-bit resolution
01 - 20-bit resolution
10 - 16-bit resolution
11 - Reserved
DS469PP4
19
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