CDB8415A(2002) Ver la hoja de datos (PDF) - Cirrus Logic
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CDB8415A Datasheet PDF : 36 Pages
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CS8405A
SWITCHING CHARACTERISTICS - CONTROL PORT - SPI MODE
(TA = 25 °C for suffixes ‘CS’ &’CZ’, TA = -40 to 85°C for ‘IS’ & ‘IZ’ ; VD+ = 5V±10%, VL+ = 3/5V ±5/10%, Inputs:
Logic 0 = 0 V, Logic 1 = VL+; CL = 20 pF)
Parameter
Symbol Min Typ Max Units
CCLK Clock Frequency
CS High Time Between Transmissions
CS Falling to CCLK Edge
CCLK Low Time
CCLK High Time
CDIN to CCLK Rising Setup Time
CCLK Rising to DATA Hold Time
CCLK Falling to CDOUT Stable
Rise Time of CDOUT
Fall Time of CDOUT
Rise Time of CCLK and CDIN
Fall Time of CCLK and CDIN
(Note 10)
fsck
0
-
6.0
MHz
tcsh
1.0
-
-
µs
tcss
20
-
-
ns
tscl
66
-
-
ns
tsch
66
-
-
ns
tdsu
40
-
-
ns
(Note 11)
tdh
15
-
-
ns
tpd
-
-
50
ns
tr1
-
-
25
ns
tf1
-
-
25
ns
(Note 12)
tr2
-
-
100
ns
(Note 12)
tf2
-
-
100
ns
Notes: 10.
If Fs is lower than 46.875 kHz, the maximum CCLK frequency should be less than 128 Fs. This is
dictated by the timing requirements necessary to access the Channel Status and User Bit buffer
memory. Access to the control register file can be carried out at the full 6 MHz rate. The minimum
allowable input sample rate is 8 kHz, so choosing CCLK to be less than or equal to 1.024 MHz should
be safe for all possible conditions.
11. Data must be held for sufficient time to bridge the transition time of CCLK.
12. For fsck <1 MHz.
CS
t css
t scl t sch
t csh
CCLK
t r2
t f2
CDIN
CDOUT
t dsu
t dh
t pd
Figure 3. SPI Mode timing
DS469PP4
7
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