CS8405A-CS Ver la hoja de datos (PDF) - Cirrus Logic
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CS8405A-CS Datasheet PDF : 37 Pages
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CS8405A
SWITCHING CHARACTERISTICS - CONTROL PORT - I²C MODE
(Note 14, Inputs: Logic 0 = 0 V, Logic 1 = VL+; CL = 20 pF)
Parameter
Symbol Min Typ Max
SCL Clock Frequency
fscl
-
-
100
Bus Free Time Between Transmissions
tbuf
4.7
-
-
Start Condition Hold Time (prior to first clock pulse)
thdst
4.0
-
-
Clock Low Time
tlow
4.7
-
-
Clock High Time
thigh
4.0
-
-
Setup Time for Repeated Start Condition
tsust
4.7
-
-
SDA Hold Time from SCL Falling
(Note 15) thdd
0
-
-
SDA Setup Time to SCL Rising
tsud
250
-
-
Rise Time of Both SDA and SCL Lines
tr
-
-
25
Fall Time of Both SDA and SCL Lines
tf
-
-
25
Setup Time for Stop Condition
tsusp
4.7
-
-
Notes: 14. I²C protocol is supported only in VL+ = 5.0 V mode.
15. Data must be held for sufficient time to bridge the 300 ns transition time of SCL.
Units
kHz
µs
µs
µs
µs
µs
µs
ns
ns
ns
µs
Stop Start
Repeated
Start
SDA
SCL
t buf
t hdst
t high
t hdst
tf
t low t hdd
t sud
t sust
tr
Figure 4. I²C Mode timing
Stop
t susp
DS469F2
9
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