CS8413-CS Ver la hoja de datos (PDF) - Cirrus Logic
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CS8413-CS Datasheet PDF : 38 Pages
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CS8413 CS8414
and output random data if ROER is not set. The
conditions that activate ERF are those reported in
SR2 and enabled in IER2. Figure 10 illustrates the
modes selectable by SDF2-SDF0 and FSF1-FSF0.
MSTR, which in most applications will be set to
one, determines whether FSYNC and SCK are out-
puts (MSTR = 1) or inputs (MSTR = 0). When
FSYNC and SCK are inputs (slave mode) the audio
data can be read twice or missed if the device con-
trolling FSYNC and SCK is on a different time-
base than the CS8413. If the audio data is read
twice or missed, the SLIP bit in SR1 is set. SCED
selects the SCK edge to output data on. SCED high
causes data to be output on the falling edge, and
SCED low causes data to be output on the rising
edge.
FSF MSTR
10 (bit)
00 0 FSYNC Input
01 0 FSYNC Input
10 0 FSYNC Input
11 0 FSYNC Input
00 1 FSYNC Output
01 1 FSYNC Output
10 1 FSYNC Output
11 1 FSYNC Output
SDF
210 (bit) Name
000
MSB First - 32
001
MSB Last
011
LSB Last - 16
101
LSB Last - 18
111
LSB Last - 20
SPECIAL MODES:
SDF
210 MSTR Name
100 0 Async SCK
110 0 MSB First - 24
010 0 MSB First - 16
010*† 1 NRZ Data
100* 1 Bi-Phase Data
32 Bits
32 Bits
16 Clocks
16 Clocks
16 Clocks
16 Clocks
32 Clocks
32 Clocks
MSB
MSB
LSB
LSB
LSB
32 Clocks
Left Sample
24 Bits, Incl. Aux
LSB
24 Bits, Incl. Aux
LSB
16 Bits
MSB
18 Bits
MSB
20 Bits
MSB
MSB
MSB
LSB
LSB
LSB
32 Clocks
Right Sample
24 Bits, Incl. Aux
LSB
24 Bits, Incl. Aux
LSB
16 Bits
MSB
18 Bits
MSB
20 Bits
MSB
MSB
MSB
LSB
LSB
LSB
24 Bits, Incl. Aux
24 Bits, Incl. Aux
MSB
MSB
MSB
LSB
24 Bits, Incl. Aux
16 Bits
MSB
LSB MSB
LSB MSB
LSB
24 Bits, Incl. Aux
16 Bits
MSB
LSB MSB
LSB MSB
32 Bits
AUX LSB
MSB VUCP
32 Bits
AUX LSB
MSB VUCP
AUX
Bi-Phase Mark Data
Bi-Phase Mark Data
* Error flags are not accurate in these modes
† FSYNC is inverted FSF = 11
Figure 10. CS8413 Serial Port SDATA and FSYNC Timing
DS240F1
13
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