CS8414-CS Ver la hoja de datos (PDF) - Cirrus Logic
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CS8414-CS Datasheet PDF : 38 Pages
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CS8413 CS8414
RXP 9
RXN 10
VA+ FILT AGND MCK
22 20 21 19
Clock & Data
Recovery
Bi-phase
Decoder
De-Multiplexor
Audio
Serial
Port
11 FSYNC
12 SCK
26 SDATA
VD+ 7
DGND 8
crc
check
Frequency
Comparator
Figure 4. CS8413 Block Diagram
Control
Registers
2X8
aux
user
C.S.
Buffer
Memory
28 X 8
slipped
parity
validity
crc
coding
no lock
IEnable
&
Status
4X8
48
13
A4/ A0- D0-
FCK A3 D7
14 INT
25 ERF
24 CS
23 RD/WR
Status and IEnable Registers
The status and interrupt enable registers occupy the
same address space. The IER/SR bit in control reg-
ister 1 selects whether the status registers
(IER/SR = 0) or the IEnable registers (IER/SR = 1)
occupy addresses 0 and 1. Upon power-up, the con-
trol and IEnable registers contain all zeros; there-
fore, the status registers are visible and all
interrupts are disabled. The IER/SR bit must be set
to make the IEnable registers visible.
Status register 1 (SR1), shown in Figure 6, reports
all the conditions that can generate a low pulse four
SCLK cycles wide on the interrupt pin (INT). The
three least significant bits, FLAG2-FLAG0, are
used to monitor the ram buffer. These bits continu-
ally change and indicate the position of the buffer
pointer which points to the buffer memory location
currently being written. Each flag has a corre-
sponding interrupt enable bit in IEnable register 1
which, when set, allows a transition on the flag to
generate a pulse on the interrupt pin. FLAG0 and
FLAG1 cause interrupts on both edges whereas
FLAG2 causes an interrupt on the rising edge only.
Further information, including timing, on the flags
can be found in the Buffer Memory section.
The next five bits; ERF, SLIP, CCHG,
CRCE/CRC1, and CSDIF/CRC2, are latches
which are set when their corresponding conditions
occur, and are reset when SR1 is read. Interrupt
DS240F1
9
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