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SI5328

ITU-T G.8262 SYNCHRONOUS ETHERNET JITTER-ATTENUATING CLOCK MULTIPLIER

Silicon Laboratories 

Si5328

Table 2. DC Characteristics

(VDD = 2.5 V ±10% or 3.3 V ±10%, TA = –40 to 85 °C)

Parameter

Supply Current1

Symbol

Test Condition

Min

Typ

IDD

LVPECL Format

—

251

808 MHz Out

Both CKOUTs Enabled

LVPECL Format

808 MHz Out

1 CKOUT Enabled

—

217

CMOS Format

—

204

25 MHz Out

Both CKOUTs Enabled

CMOS Format

25 MHz Out

1 CKOUT Enabled

—

194

Disable Mode

—

165

Max

Unit

279

mA

243

mA

234

mA

220

mA

—

mA

CKINn Input Pins2

Input Common Mode

Voltage (Input Thresh-

old Voltage)

VICM

2.5 V ± 10%

3.3 V ± 10%

1

—

1.7

V

1.1

—

1.95

V

Input Resistance

CKNRIN

Single-ended

20

40

60

k

Single-Ended Input

Voltage Swing

VISE

(See Absolute Specs)

fCKIN < 212.5 MHz

0.2

—

See Figure 1.

fCKIN > 212.5 MHz

0.25

—

See Figure 1.

—

VPP

—

VPP

Differential Input

VID

Voltage Swing

(See Absolute Specs)

fCKIN < 212.5 MHz

0.2

—

See Figure 1.

fCKIN > 212.5 MHz

0.25

—

See Figure 1.

—

VPP

—

VPP

Notes:

1. Current draw is independent of supply voltage

2. No under- or overshoot is allowed.

3. LVPECL, CML, LVDS and low-swing LVDS measured with Fo = 312.5 MHz.

4. This is the amount of leakage that the 3-Level inputs can tolerate from an external driver. See Si53xx Family

Reference Manual for more details.

Rev. 1.0

5

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