![](/html/ZARLINK/609180/page8.png)
SL6140
Figure 12 - 3rd Order Intercept Point Against Gain Reduction At 100.0MHz and 104.0MHz
1nF
6
2
1
L1
5
8
7
43
1nF
+12V
L2
O/P
VARIABLE CAPS 3-25pF
L1 7 TURNS # 18 SWG
L2 6 TURNS # 16 SWG
8mm DIA 16mm LONG
14mm DIA 19mm LONG
Figure 13 - 50MHz Noise Figure Test Circuit
8