RC5060 Ver la hoja de datos (PDF) - Fairchild Semiconductor
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RC5060 Datasheet PDF : 15 Pages
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PRODUCT SPECIFICATION
RC5060
able to awaken from sleep when the modem receives incom-
ing data, then that slot must be powered from dual, because
main power is off. Other slots not requiring dual power can
be configured using the control signals.
3.3V dual is generated by two MOSFETs, one from +3.3V
main, the other from +5V standby, as shown in Figures 4 or
5. When main power is present, the MOSFET Q3 is turned
on as a switch, so that input and output are connected
together. When main power is absent, the MOSFET Q4 is
controlled by the RC5060 as a linear regulator, generating a
regulated 3.3V from +5V standby. As with the 5V dual, the
MOSFET Q3 must be connected as shown in the figures, to
avoid back-feed.
The state of the MOSFETs is controlled by the SLP_S3# and
PWROK lines, as shown in Figure 3. When both SLP_S3#
and PWROK are asserted, the main switch is on, and the linear
regulator is off. If either line is de-asserted, the main switch
is off and the linear regulator is on.
Q3 and Q4 as shown in Tables 3 or 4 have different RDS,on
ratings. In a typical system, it is anticipated that full-power
current will be about 2.4A maximum, and standby current
will be about 500mA maximum. The difference in maximum
currents means that Q4 can be a less expensive device than Q3.
The design of the linear regulator for the 3.3V Dual necessi-
tates a minimum load current of 50mA. Furthermore, in
order to guarantee stable operation, the output capacitor on
the 3.3V Dual must have a minimum ESR as shown in Fig-
ure 7. The hatched region shows acceptable values of ESR
vs. output capacitance. Values of the output capacitor less
than 47µF or greater than 300µF are not recommended.
300
200
ESR (mΩ)
100
47 100
200
C (µF)
300 330 400
Figure 7. Recommended C vs. ESR for
Stable Operation of the 3.3V Dual
3.3V SDRAM Output
3.3V SDRAM output is intended to provide power to
SDRAM memory. Most systems will use this power. Those
systems using RAMBUS may also use the SDRAM power,
possibly piped to the same slots, to ensure backward compat-
ibility or even mixed operation of SDRAM with RAMBUS.
3.3V SDRAM is generated by one external MOSFET switch
from +3.3V main, and one linear regulator internal to the
RC5060 from +5V standby, as shown in Figures 4 or 5, and
in the block diagram on the front page. When main power is
present, the MOSFET Ql is turned on as a switch, so that
input and output are connected together. When main power
is absent, the internal linear regulator is on, generating a reg-
ulated 3.3V from +5V standby. As with the other duals, the
MOSFET Ql must be connected as shown in the figures, to
avoid back-feed.
The state of the external MOSFET and the internal linear
regulator is controlled by the SLP_S3# and PWROK lines,
and additionally the SLP_S5# line, as shown in Figure 3.
When SLP_S5# is de-asserted, both the external MOSFET
and the internal linear regulator are off, and there is no out-
put voltage on the 3.3V SDRAM line.
If the SLP_S5# line is asserted, the 3.3V SDRAM output is
on. In this condition, if either the SLP_S3# or the PWROK
line, or both, are de-asserted, the linear regulator is on and
the MOSFET is off. Only in the case if both the SLP_S3#
and the PWROK lines are asserted, the MOSFET is on and
the linear regulator is off.
In a typical system, it is anticipated that standby current will
be about 100mA maximum. Full power current will be as
high as 4.8A maximum, so that Ql must have a low RDS,on
in order to prevent excessive voltage drop across it.
2.5V Dual Output
The 2.5V dual output is intended to provide power to RAM-
BUS memory. Only high-end systems will use this power.
Those systems using RAMBUS may also use the SDRAM
power, possibly piped to the same slots, to ensure backward
compatibility or even mixed operation of SDRAM with
RAMBUS.
2.5V dual is generated by one external NPN bipolar acting as
a linear regulator from +3.3V main, and one linear regulator
internal to the RC5060 from +5V standby, as shown in Fig-
ure 4, and in the block diagram on the front page. When
main power is present, the NPN Q2 linear regulates, and
when main power is absent, the internal linear regulator is
on. Q2 cannot be substituted with a MOSFET. If used in one
direction, the MOSFET’s body diode would permit back-
feed; if used in the other direction, it would short-circuit the
linear regulator action.
2.5V dual output is controlled in the same way and by the
same lines as the 3.3V SDRAM output. In a typical system,
it is anticipated that standby current will be a maximum of
144mA, and full-power current may be as high as 2A. This
places some significant constraints on the selection of Q2.
Since its input may be as low as (3.3V - 5%) = 3.135V, there
is only 3.135V -2.5V = 635mV of VCE headroom for its
REV. 1.0.2 9/14/01
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