HIP6021A(1999) Ver la hoja de datos (PDF) - Intersil
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HIP6021A Datasheet PDF : 16 Pages
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HIP6021A
R3, C1, C2, and C3) in Figure 7. Use these guidelines for
locating the poles and zeros of the compensation network:
1. Pick Gain (R2/R1) for desired converter bandwidth
2. Place 1ST Zero Below Filter’s Double Pole (~75% FLC)
3. Place 2ND Zero at Filter’s Double Pole
4. Place 1ST Pole at the ESR Zero
5. Place 2ND Pole at Half the Switching Frequency
6. Check Gain against Error Amplifier’s Open-Loop Gain
7. Estimate Phase Margin - Repeat if Necessary
LIN
+5VIN
CIN
+3.3VIN
+12V
CVCC
VCC GND
OCSET1
Q3
VOUT2
DRIVE2
UGATE1
COUT2
PHASE1
VOUT3
LGATE1
SS
CSS
HIP6021A
COCSET1
ROCSET1
Q1
LOUT1
VOUT1
COUT1
Q2
CR1
VOUT4
COUT3
Q4
DRIVE3 DRIVE4
PGND
COUT4
Q5
+3.3VIN
KEY
ISLAND ON POWER PLANE LAYER
ISLAND ON CIRCUIT PLANE LAYER
VIA CONNECTION TO GROUND PLANE
FIGURE 7. PRINTED CIRCUIT BOARD POWER PLANES AND
ISLANDS
Figure 9 shows an asymptotic plot of the DC-DC converter’s
gain vs frequency. The actual Modulator Gain has a high gain
peak dependent on the quality factor (Q) of the output filter,
which is not shown in Figure 8. Using the above guidelines
should yield a Compensation Gain similar to the curve plotted.
The gain. Check the compensation gain at FP2 with the
capabilities of the error amplifier. The Closed Loop Gain is
constructed on the log-log graph of Figure 9 by adding the
Modulator Gain (in dB) to the Compensation Gain (in dB). This
is equivalent to multiplying the modulator transfer function to the
compensation transfer function and plotting the gain.
The compensation gain uses external impedance networks
ZFB and ZIN to provide a stable, high bandwidth (BW) overall
loop. A stable control loop has a gain crossing with
-20dB/decade slope and a phase margin greater than 45
degrees. Include worst case component variations when
determining phase margin.
OSC
∆VOSC
PWM
COMP
-
+
VIN
DRIVER
LO
DRIVER
PHASE CO
VOUT
ZFB
VE/A
-
+
ZIN
ERROR REFERENCE
AMP
ESR
(PARASITIC)
DETAILED COMPENSATION COMPONENTS
C2
C1 R2
ZFB
VOUT
ZIN
C3 R3
R1
COMP
FB
-
+
HIP6021A
DACOUT
FIGURE 8. VOLTAGE-MODE BUCK CONVERTER
COMPENSATION DESIGN
Compensation Break Frequency Equations
FZ1 = 2----π-----×-----R---1--2-----×----C-----1--
FZ2 = 2----π-----×-----(--R-----1-----+-1----R-----3---)----×-----C-----3-
FP1
=
---------------------------1---------------------------
2
π
×
R2
×
C-C----11-----+×-----CC-----22--
FP2 = -2---π-----×-----R---1--3-----×----C-----3--
FZ1
FZ2 FP1 FP2
OPEN LOOP
100
ERROR AMP GAIN
80
20
log
V--V---P-I--N-P---
60
40
COMPENSATION
GAIN
20
0
-20
20log RR-----21--
MODULATOR
-40
GAIN FLC FESR
-60
10
100
1K
10K 100K
FREQUENCY (Hz)
CLOSED LOOP
GAIN
1M 10M
FIGURE 9. ASYMPTOTIC BODE PLOT OF CONVERTER GAIN
12
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