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HIP6021A
(Rev.:1999)

Advanced PWM and Triple Linear Power Controller

Intersil 

HIP6021A

PGOOD

0V

SOFT-START

(1V/DIV)

0V

OUTPUT

VOLTAGES

(0.5V/DIV)

VOUT2 (= 3.3VIN)

VOUT1 (DAC = 2.5V)

VOUT4 (= 1.8V)

VOUT3 (= 1.5V)

0V

T0 T1

T2

T3

T4

TIME

FIGURE 2. SOFT-START INTERVAL

The remaining outputs are also programmed to follow the

SS pin voltage. The PGOOD signal toggles ‘high’ when all

output voltage levels have exceeded their under-voltage

levels. The waveform for VOUT2 represents the case where

SELECT is held ‘high’. The AGP bus voltage is controlled in

the same manner as the other linear regulators during the

softstart sequence. Once the softstart sequence is

complete (T4), the gate of the external pass device is fully

enhanced and VOUT2 tracks the 3.3VIN voltage. See the

Soft-Start Interval section under Applications Guidelines for

a procedure to determine the soft-start interval.

Fault Protection

All four outputs are monitored and protected against extreme

overload. A sustained overload on any output or an over-

voltage on VOUT1 output (VSEN1) disables all outputs and

drives the FAULT/RT pin to VCC.

Figure 3 shows a simplified schematic of the fault logic. An

over-voltage detected on VSEN1 immediately sets the fault

latch. A sequence of three over-current fault signals also

sets the fault latch. The over-current latch is set dependent

upon the states of the over-current (OC), linear under-

voltage (LUV) and the soft-start signals. A window

comparator monitors the SS pin and indicates when CSS is

fully charged to 4V (UP signal). An under-voltage on either

linear output (VSEN2, VSEN3, or VSEN4) is ignored until

after the soft-start interval (T4 in Figure 2). This allows

VOUT2, VOUT3, and VOUT4 to increase without fault at start-

up. Cycling the bias input voltage (+12VIN on the VCC pin off

then on) resets the counter and the fault latch.

LUV

OC1

0.15V +

-

SS

+

4V -

OV

OVER-

CURRENT

LATCH

SQ

INHIBIT

R

COUNTER

R

FAULT VCC

LATCH

UP

SQ

POR

R

FAULT

FIGURE 3. FAULT LOGIC - SIMPLIFIED SCHEMATIC

Over-Voltage Protection

During operation, a short on the upper MOSFET of the PWM

regulator (Q1) causes VOUT1 to increase. When the output

exceeds the over-voltage threshold of 115% of DACOUT, the

over-voltage comparator trips to set the fault latch and turns

Q2 on. This blows the input fuse and reduces VOUT1. The

fault latch raises the FAULT/RT pin to VCC.

A separate over-voltage circuit provides protection during

the initial application of power. For voltages on the VCC pin

below the power-on reset (and above ~4V), the output level

is monitored for voltages above 1.3V. Should VSEN1 exceed

this level, the lower MOSFET, Q2 is driven on.

Over-Current Protection

All outputs are protected against excessive over-currents.

The PWM controller uses the upper MOSFET’s

on-resistance, rDS(ON) to monitor the current for protection

against shorted output. All linear controllers monitor their

respective VSEN pins for under-voltage events to protect

against excessive currents.

Figure 4 illustrates the over-current protection with an

overload on OUT1. The overload is applied at T0 and the

current increases through the inductor (LOUT1). At time T1,

the OVER-CURRENT comparator trips when the voltage

across Q1 (iD • rDS(ON)) exceeds the level programmed by

ROCSET. This inhibits all outputs, discharges the soft-start

capacitor (CSS) with a 10mA current sink, and increments

the counter. CSS recharges at T2 and initiates a soft-start

cycle with the error amplifiers clamped by soft-start. With

OUT1 still overloaded, the inductor current increases to trip

the over-current comparator. Again, this inhibits all outputs,

but the soft-start voltage continues increasing to 4V before

discharging. The counter increments to 2. The soft-start

cycle repeats at T3 and trips the over-current comparator.

The SS pin voltage increases to 4V at T4 and the counter

increments to 3. This sets the fault latch to disable the

converter. The fault is reported on the FAULT/RT pin.

The linear controllers operate in the same way as the PWM

in response to over-current faults. The differentiating factor

8

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