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RL56CSMV/6-35LP

AnyPort™ Multi-Service Access Processor

Conexant Systems 

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Technical Specifications

General Description

The RL56CSMV/6 provides the processing core for six

channels of a central site Remote Access Server

supporting high speed T1/E1/PRI digital lines. The OEM

adds two oscillators, SDRAM, and discrete components to

complete the Multi-Service Access Processor system.

The access processor includes a full-featured, self-

contained data/fax/Voice modem solution shown in Figure

1. Data modem handshake, fax modem protocol, voice

codecs, and ISDN data connection functions are

supported and controlled through the AT command set.

Digital Data Pump (DDP)

The DDP is a +3.3V/+2.5V Conexant data pump

supporting PSTN data/fax modem operation, ISDN B

Channel call termination mode, and voice

coding/decoding. The DDP executes internal code

including downloadable modules from on-chip memory.

Digital data transfers serially between the T1/E1 framer

device and the DDP at a data rate up to 8.192 Mbps. The

T1/E1 framing device provides a strobe signal and the

DDP TSA logic detects where the data for the channel

starts in the serial TDM data stream using a

programmable counter. The DDP performs PCM µ-law or

A-law conversion and synchronizes with an external

network clock.

ARM Microcontroller (MCU)

The ARM MCU performs the command processing and

interfaces to the central site system controller via a 16-bit

parallel host interface. Two 64-word deep FIFOs are used

for improved data throughput between the access

processor and system controller. This single powerful

RISC processor controls six separate channels. A

SDRAM loader is available to support download from the

central site system controller on startup, if desired.

Access Processor Operation

In data modem modes, each channel can independently

connect to PSTN data modems at rates up to 56 kbps or

ISDN terminal adapters at rates up to 64 kbps. A

downloadable architecture allows for software download.

For PSTN modems, complete handshake and data rate

negotiations are performed. By optimizing the modem

configuration for line conditions, the DDP can connect at

the highest data rate that the channel can support from 56

kbps to 300 bps with automatic fallback. Automode

operation in V.34 is provided in accordance with PN3320

and in V.32 bis in accordance with PN2330. All tone and

pattern detection functions required by the applicable ITU

or Bell standard are supported. Asynchronous to

synchronous conversion is supported inside the controller

to ease PPP processing in PSTN data mode.

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When the remote end is an ISDN terminal adapter, the

RL56CSMV/6 provides HDLC control including HDLC

Flag generation/detection, bit stuffing/extraction, and CRC

generation/checking. V.120, V.110, and LAP-B X.75 are

also supported. V.120 is a standard for encapsulating

asynchronous data communications traffic into ISDN data

streams.

In fax modem mode, the RL56CSMV/6 supports Group 3

facsimile send and receive speeds of 33600, 31200,

28800, 26400, 24000, 21600, 19200, 16800, 14400,

12000, 9600, 7200, 4800, and 2400 bps. Fax modem

modes support T.30 and T.38 fax requirements. Fax data

transmission and reception performed by the access

processor are controlled and monitored through the EIA-

578 Class 1 and Class 2 command interface. Both

transmit and receive fax data are buffered within the

access processor.

In Voice mode, the CSMV/6 encodes PCM audio data

from the line into Real-Time Protocol (RTP) packets for

the Host, and decodes RTP packets from the Host, to

output PCM audio data to the line. In Voice mode, DTMF

digits can be detected and transmitted, and a Voice

Activity Detector can be enabled.

Access Processor Firmware

Access processor firmware performs processing of

general modem control, command sets, error correction

and data compression, fax class 1 and class 2, voice

coding and decoding (optional), and central site system

controller interface functions.

The firmware is provided in object code form for executing

from external SDRAM after download on startup using the

ROM-coded Boot Loader. Equipment designers can add

their own functions in firmware using commonly available

development tools and the C programming language.

Hardware Interface Signals

The RL56CSMV/6 interface is illustrated in Figure 2.

The 371-pin BGA package identifying pin locations for the

RL56CSMV/6 is shown in Figure 3.

The RL56CSMV/6 pin signals in the 371-pin BGA are

listed by location in Table 2 and by interface in Table 3.

The RL56CSMV/6 application signals are listed by

interface in Table 4.

Additional Information

Additional information is described in the RL56CSMV/6

AnyPort Multi-Service Access Processor Hardware

Interface Description (Order No. 100469, formerly 1192),

the RL56DDP Designer’s Guide (Doc. No. 1141), the

CSMV/6 AnyPort™ Multi-Service Access Processor

Software Interface Description (Doc. No. 100597, formerly

1148), and the Command Reference Manual (Doc. No.

100468, formerly 1195).

100467E

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