HI-8582 Ver la hoja de datos (PDF) - Holt Integrated Circuits

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HI-8582

ARINC 429 System on a Chip

Holt Integrated Circuits 

HI-8582, HI-8583

FUNCTIONAL DESCRIPTION (cont.)

RECEIVER PARITY

The 32nd bit of received ARINC words stored in the receive FIFO

is used as a Parity Flag indicating whether good Odd parity is

received from the incoming ARINC word.

ARINC words which do not meet the necessary 9th and 10th

ARINC bit or label matching are ignored and are not loaded into

the receive FIFO. The following table describes this operation.

Odd Parity Received

The parity bit is reset to indicate correct parity was received

and the resulting word is written to the receive FIFO.

Even Parity Received

The receiver sets the 32nd bit to a “1”, indicating a parity error

and the resulting word is then written to the receive FIFO.

Therefore, the 32nd bit retrieved from the receiver FIFO will always

be “0” when valid (odd parity) ARINC 429 words are received.

RETRIEVING DATA

Once 32 valid bits are recognized, the receiver logic generates an

End of Sequence (EOS). Depending upon the state of control

register bits CR2-CR11, the received ARINC 32-bit word is then

checked for correct decoding and label matching before being

loaded into the 32 x 32 receive FIFO.

CR2(3) ARINC word CR6(9) ARINC word

matches

bits 9,10

label

match

CR7,8 (10,11)

0

X

0

X

1

No

0

X

1

Yes

0

X

0

X

1

No

0

X

1

Yes

1

Yes

1

No

1

No

1

Yes

1

No

1

No

1

Yes

1

Yes

FIFO

Load FIFO

Ignore data

Load FIFO

Ignore data

Load FIFO

Ignore data

Ignore data

Ignore data

Load FIFO

SEL

MUX

CONTROL

EN

TO PINS

32 TO 16 DRIVER

R/W

CONTROL

CONTROL

BITS

HF

FF

D/R

FIFO

LOAD

CONTROL

CONTROL

BIT

32 X 32

FIFO

/ LABEL /

DECODE

COMPARE

CONTROLBITS

CR0, CR14

CLOCK

OPTION

16 x 8

LABEL

MEMORY

EOS

32 BIT SHIFT REGISTER

DATA PARITY

CHECK

BIT CLOCK

32ND

BIT

BIT

COUNTER

AND

END OF

SEQUENCE

ONES

NULL

SHIFT REGISTER

SHIFT REGISTER

WORD GAP

WORD GAP

TIMER

BIT CLOCK

START

SEQUENCE

CONTROL

END

CLOCK

CLK

ZEROS

SHIFT REGISTER

ERROR

DETECTION

ERROR

CLOCK

FIGURE 2. RECEIVER BLOCK DIAGRAM

HOLT INTEGRATED CIRCUITS

5

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