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GM16C550

ASYNCHRONOUS COMMUNICATIONS ELEMENT WITH FIFOs

Hynix Semiconductor 

The transmitter FIFO empty indications will be delayed 1

character time minus the last stop bit time whenever the

following occurs: THRE = 1 and there have not been at least

two bytes at the same time in the transmit FIFO, since the last

THRE = 1. The first transmitter interrupt affect changing

FCR0 will be immediate, if it is enabled.

Character timeout and RCVR FIFO trigger level interrupts

have the same priority as the current received data available

interrupt; XMIT FIFO empty has the same priority as the

current transmitter holding register empty interrupt.

FIFO POLLED MODE PRERATION

With FCRQ = 1 resetting IER0, IER1, IER2, IER3 or all to

zero puts the RCVR and MITTER are controlled separately

either one or both can be in the polled mode of operation.

GM16C550

In this mode the user’s program will check RCVR and

XMITTER status via the LSR. As stated previously:

LSR0 will be set as long as there is one byte in the RCR FIFO.

LSR1 to LSR4 will specify which error(s) has occurred.

Character error status is handled the same way when in the

interrupt mode, the IIR is not affected since IER2=0.

LSR5 will indicate when the XMIT FIFO is empty.

LSR6 will indicate that both the XMIT FIFO and shift

register are empty.

LSR7 will indicate whether there are any errors in the RCVR

FIFO.

There is no trigger level reached or timeout condition

indicated in the FIFO polled Mode, however, the RCVR and

XMIT FIFOs still fully capable of holding characters.

Application Circuit

SYSTEM BUS

A0 –A23

CPU

D0 –D15

RESET

LATCH

ADDRESS

DECODER

+5

DATA D0 –D7

BUFFER

tOR

tCW

D0-D15

A0 –A2

XTAL1

XTAL2

CS2

CS1

CS0

RCLK

MR

SOUT

GM16C550 SIN

D0 –D7

RST

DTR

DSR

DISTR

DCD

CTS

DOSTR

DISTR

DOSTR

ADS

RI

INTRPT

TXRDY

DDIS

RXRDY

EIA

DRIVERS

RS-232-C D

INTERFACE

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