PM7375 Ver la hoja de datos (PDF) - PMC-Sierra
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PM7375 Datasheet PDF : 430 Pages
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DATA SHEET
PMC-931127
11
PM7375 LASAR-155
ISSUE 6
LOCAL ATM SAR & PHYSICAL LAYER
10.4.41 REGISTER 0X3A8: PCID TX DESCRIPTOR REFERENCE LOW PRIORITY
READY QUEUE READ....................................................................................298
10.4.42 REGISTER 0X3AC: PCID TX DESCRIPTOR REFERENCE LOW PRIORITY
READY QUEUE END ......................................................................................299
10.4.43 REGISTER 0X3B0: PCID MAX TX SDU LENGTH..........................................300
10.4.44 REGISTER 0X3B4: PCID RAS AND TAS FIFO POINTERS ...........................301
10.4.45 REGISTER 0X3C8: PCID RAM INDIRECT CONTROL ..................................303
10.4.46 REGISTER 0X3CC: PCID RAM INDIRECT DATA LOW WORD......................305
10.4.47 REGISTER 0X3D0: PCID RAM INDIRECT DATA HIGH WORD .....................306
10.4.48 REGISTER 0X3D4: PCID HOST WRITE MAILBOX CONTROL .....................307
10.4.49 REGISTER 0X3D8: PCID HOST WRITE MAILBOX DATA ..............................308
10.4.50 REGISTER 0X3E0: PCID HOST READ MAILBOX CONTROL.......................309
10.4.51 REGISTER 0X3E4: PCID HOST READ MAILBOX DATA................................310
PCI CONFIGURATION REGISTER DESCRIPTIONS .................................................................311
11.1.1 PCI CONFIGURATION REGISTER MEMORY MAP ......................................311
11.1.2 REGISTER 0X00 (0X00): VENDOR IDENTIFICATION / DEVICE
IDENTIFICATION ............................................................................................312
11.1.3 REGISTER 0X01 (0X04): COMMAND / STATUS............................................313
11.1.4 REGISTER 0X02 (0X08): REVISION IDENTIFIER / CLASS CODE...............317
11.1.5 REGISTER 0X03 (0X0C): CACHE LINE SIZE / LATENCY TIMER / BIST /
HEADER TYPE ...............................................................................................318
11.1.6 REGISTER 0X04 (0X10): LASAR-155 MEMORY BASE ADDRESS REGISTER
........................................................................................................................319
11.1.7 REGISTER 0X05 (0X14): EXTERNAL DEVICE MEMORY BASE ADDRESS
REGISTER......................................................................................................321
11.1.8 REGISTER 0X0C (0X30): EXPANSION ROM BASE ADDRESS ....................323
11.1.9 REGISTER 0X0F (0X3C): INTERRUPT LINES / INTERRUPT PINS / MIN_GNT /
MAX_LAT ........................................................................................................324
PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS’ INTERNAL USE xi
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