PCF50732H/F1 Ver la hoja de datos (PDF) - Philips Electronics

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PCF50732H/F1

Baseband and audio interface for GSM

Philips Electronics 

Philips Semiconductors

Baseband and audio interface for GSM

Objective specification

PCF50732

handbook, full pagewidth

ADI

ACLK

ASI

AFS

ADO

16-bit, 8 kHz

VOICE BAND SIGNAL PROCESSOR

TXPGA/LIM

SidePGA

RX/TX

FILTER

RXVOL

RXPGA/LIM

RRAM

IRAM

DECIMATOR

TX_BS

(transmit bitstream)

1-bit, 1 MHz

NOISE

SHAPER

MGR992

RX_BS

(receive bitstream)

Fig.7 Block diagram of the voice band signal processor.

10.3.1 VOLUME CONTROL BLOCK

The volume control block contains the RXPGA, SidePGA,

TXPGA and both limiter blocks. The possible settings can

be found in the description of the CSI block. All digital

volume control blocks, i.e. RXPGA, SidePGA, and

TXPGA, will allow settings from +6 to −30 dB and mute in

64 steps. However, not all combinations of settings for

these blocks will be meaningful. The limiter will always clip

signals with overflow to the maximum or minimum

allowable value.

10.3.2 AUDIO SERIAL INTERFACE (ASI) BLOCK

The ASI is the voice band serial interface which provides

the connection for the exchange of PCM data in both

receive and transmit directions, between the baseband

digital signal processor and the PCF50732. The data is

coded in 16-bit linear PCM twos complement words.

A frame start is defined by the first falling edge of ACLK

after a rising AFS. This first falling edge is used to clock in

the first data bit on both the baseband and the DSP device.

Data on pin ADI is clocked in (MSB first) on the falling edge

of the ACLK clock. Data is clocked out (MSB first) on pin

ADO on the rising edge of the ACLK clock.

Pin ADO is put in 3-state after the LSB of the transmit

word, independent of the length of the AFS pulse. If the

channel position 0 (see Section 10.3.2.1) is selected, then

the MSB must be output directly after AFS becomes a

logic 1, even if no rising edge on ACLK has been given yet.

The following modes of operation are programmable:

channel position and ACLK clock mode.

10.3.2.1 Channel position mode

Depending on a programmable register value n

(n = 0 to 15) one of 16 channels can be selected (see

Table 22). The ASI can add a delay of 16 × n-bit clocks

between the assertion of AFS and the start of the MSB of

the PCM values. This delay is independently

programmable for transmit and receive mode.

10.3.2.2 ACLK clock mode

Single or double clock mode can be selected. Double clock

mode implies two clock pulses per data bit and is used for

communication with IOM2 compatible devices. In double

clock mode data must be output on the first rising edge and

be read on the last falling edge.

1999 May 03

18

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