74HC/HCT4510 Ver la hoja de datos (PDF) - Philips Electronics
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74HC/HCT4510 Datasheet PDF : 12 Pages
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Philips Semiconductors
BCD up/down counter
Product specification
74HC/HCT4510
Tamb (°C)
TEST CONDITIONS
SYMBOL PARAMETER
74HCT
+25
−40 to +85
−40 to +125
UNIT VCC WAVEFORMS
(V)
min. typ. max. min. max. min. max.
trem
removal time
23 13
29
35
MR to CP
ns
4.5 Fig.10
trem
removal time
17 10
21
26
PL to CP
ns
4.5 Fig.10
tsu
set-up time
20 12
25
30
UP/DN to CP
ns
4.5 Fig.8
tsu
set-up time
CE to CP
20 6
25
30
ns
4.5 Fig.8
tsu
set-up time
Dn to PL
th
hold time
CE to CP
20 6
50
25
30
5
5
ns
4.5 Fig.11
ns
4.5 Fig.8
th
hold time
Dn to PL
50
5
5
th
hold time
0 −5
0
0
UP/DN to CP
ns
4.5 Fig.11
ns
4.5 Fig.8
fmax
maximum clock pulse 30 53
24
20
frequency
MHz 4.5 Fig.7
AC WAVEFORMS
(1) HC : VM = 50%; VI = GND to VCC.
HCT: VM = 1.3 V; VI = GND to 3 V.
Fig.7
Waveforms showing the clock (CP) to
output (Qn) and terminal count (TC)
propagation delays, the clock pulse width
and the maximum clock pulse frequency.
(1) HC : VM = 50%; VI = GND to VCC.
HCT: VM = 1.3 V; VI = GND to 3 V.
Fig.8
Waveforms showing the set-up and hold
times from count enable (CE) and
up/down (UP/DN) control inputs to the
clock pulse (CP), the propagation delays
from UP/DN, CE to TC.
December 1990
9
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