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HEF4510B

BCD up/down counter

Philips Electronics 

Philips Semiconductors

BCD up/down counter

DESCRIPTION

The HEF4510B is an edge-triggered synchronous

up/down BCD counter with a clock input (CP), an up/down

count control input (UP/DN), an active LOW count enable

input (CE), an asynchronous active HIGH parallel load

input (PL), four parallel inputs (P0 to P3), four parallel

outputs (O0 to O3), an active LOW terminal count output

(TC), and an overriding asynchronous master reset input

(MR).

Information on P0 to P3 is loaded into the counter while PL

is HIGH, independent of all other input conditions except

the MR input, which must be LOW. With PL LOW, the

counter changes on the LOW to HIGH transition of CP if

CE is LOW. UP/DN determines the direction of the count,

HIGH for counting up, LOW for counting down. When

counting up, TC is LOW when O0 and O3 are HIGH and

CE is LOW. When counting down, TC is LOW when O0 to

O3 and CE are LOW. A HIGH on MR resets the counter

(O0 to O3 = LOW) independent of all other input

conditions.

Product specification

HEF4510B

MSI

Fig.1 Functional diagram.

HEF4510BP(N): 16-lead DIL; plastic

(SOT38-1)

HEF4510BD(F): 16-lead DIL; ceramic (cerdip)

(SOT74)

HEF4510BT(D): 16-lead SO; plastic

(SOT109-1)

( ): Package Designator North America

PINNING

PL

P0 to P3

CE

CP

UP/DN

MR

TC

O0 to O3

parallel load input (active HIGH)

parallel inputs

count enable input (active LOW)

clock pulse input (LOW to HIGH,

edge triggered)

up/down count control input

master reset input

terminal count output (active LOW)

parallel outputs

FAMILY DATA, IDD LIMITS category MSI

See Family Specifications

Fig.2 Pinning diagram.

January 1995

2

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