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MM74C48N

BCD-to-7 Segment Decoder

Fairchild Semiconductor 

October 1987

Revised January 1999

MM74C48

BCD-to-7 Segment Decoder

General Description

The MM74C48 BCD-to-7 segment decoder is a monolithic

complementary MOS (CMOS) integrated circuit con-

structed with N- and P-channel enhancement transistors.

Seven NAND gates and one driver are connected in pairs

to make binary-coded decimal (BCD) data and its comple-

ment available to the seven decoding AND-OR-INVERT

gates. The remaining NAND gate and three input buffers

provide test-blanking input/ripple-blanking output, and rip-

ple-blanking inputs.

Features

s Wide supply voltage range: 3.0V to 15V

s Guaranteed noise margin: 1.0V

s High noise immunity: 0.45 VCC (typ.)

s Low power TTL compatibility:

fan out of 2 driving 74L

s High current sourcing output (up to 50 mA)

s Ripple blanking for leading or trailing zeros (optional)

s Lamp test provision

Ordering Code:

Order Number Package Number

Package Description

MM74C48N

N16E

16-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300” Wide

Connection Diagrams

Pin Assignments for DIP

Segment Identification

Numerical Designations

and Resultant Displays

Top View

© 1999 Fairchild Semiconductor Corporation DS005883.prf

www.fairchildsemi.com

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