MX614DW Ver la hoja de datos (PDF) - MX-COM Inc
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MX614DW Datasheet PDF : 19 Pages
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Bell 202 Compatible Modem
0
dBm
-10
9
MX614 PRELIMINARY INFORMATION
-20
-30
-40
450 Hz
3400 Hz
-50
-60
28 kHz
-70
10
100
1000
10000 Frequency / Hz
100000
Figure 6: Tx limits at 1200bps rate
4.8 Rx Data Retiming
This function may be used when the received data consists of 1200bps asynchronous characters, each
character consisting of one start bit followed by a minimum of 9 formatted bits as shown in the table below.
Note: Rx Data Retiming is not supported for data rates exceeding 1212bps.
Data bits
7
7
8
8
9
Parity bits
0
1
0
1
0
Stop bits
≥2
≥1
≥1
≥1
≥1
The Data Retiming block, when enabled in receive mode, extracts the first 9 bits of each character following
the start bit from the received asynchronous data stream, and presents them to the µC under the control of
strobe pulses applied to the CLK input. The timing of these pulses is not critical and they may easily be
generated by a simple software loop. This facility removes the need for a UART in the µC without incurring
an excessive software overhead.
The receive retiming block consists of two 9-bit shift registers, the input of the first is connected to the output
of the FSK demodulator and the output of the second is connected to the RXD pin. The first register is
clocked by an internally generated signal that stores the 9 received bits following the timing reference of a
high to low transition at the output of the FSK demodulator. When the 9th bit is clocked into the first register
these 9 bits are transferred to the second register, a new stop-start search is initiated and the CLK input is
sampled. If the CLK input is low at this time the RDY pin is pulled low and the first received bit is output on
the RXD pin. The CLK pin should then be pulsed high 9 times, the first 8 high to low transitions will be used
by the device to clock out the bits in the second register. The RDY output is cleared the first time the CLK
input goes high. At the end of the 9th pulse the RXD pin will be connected to the FSK demodulator output.
So to use the Data Retiming function, the CLK input should be kept low until the RDY output goes low; if the
Data Retiming function is not required the CLK input should be kept high at all times.
2000 MX-COM, INC.
www.mxcom.com Tel: 800 638 5577 336 744 5050 Fax: 336 744 5054
Doc. # 20480162.004
4800 Bethania Station Road, Winston-Salem, NC 27105 USA
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