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CMX644AD5

Bell 212A and V.22 Modem with Call Progress and DTMF

MX-COM Inc  

Bell 212A / V.22 Modem with Call Progress and DTMF

8

CMX644A Preliminary Information

4.2 UART

This block connects the µC, via the ‘C-BUS’ interface, to the received data from the PSK Demodulator and to

the transmit data input to the PSK Modulator.

As part of the UART function, this block can be programmed to convert data that is to be transmitted from

7 or 8-bit bytes to asynchronous data characters, adding Start and Stop bits, and - optionally - a parity bit to

the data before passing it to the PSK Modulator. In the receive direction the UART can extract data bits from

asynchronous characters coming from the PSK Demodulator, stripping off the Start and Stop bits, and

performing an optional Parity check on the received data, before passing the result, via the ‘C-BUS’, to the

µC. Bits 0-5 of the UART MODE Register control the number of Stop and Data bits and the Parity options for

both receive and transmit directions.

Data to be transmitted should be loaded by the µC into the TX DATA BYTE Register when the Tx Data Ready

bit (bit 1) of the FLAGS Register goes high. It will then be treated by the Tx UART block in one of two ways,

depending on the setting of bit 5 of the UART MODE Register:

1. If bit 5 of the UART MODE Register is ‘0’ (‘Sync’ mode) then the 8 bits from the TX DATA BYTE Register

will be transmitted sequentially LSB (D0) first.

2. If bit 5 of the UART MODE Register is ‘1’ (‘Async’ mode) then the 7 or 8 bits will be transmitted as

asynchronous data characters according to the following format:

One Start bit (Space).

7 or 8 Data bits from the TX DATA BYTE Register (D0-D6 or D0-D7) as determined by bit 0 of the

UART MODE Register. LSB (D0) transmitted first.

Optional Parity bit (even or odd parity) as determined by bits 1 and 2 of the UART MODE Register.

Zero, One or Two Stop bits (Mark) as determined by bits 3 and 4 of the UART MODE Register.

In both cases data will only be transmitted if bit 6 of the TX PSK MODE Register is set to ‘1’.

Failure to load the TX DATA BYTE Register with a new value when required will result in bit 2 (TX DATA

UNDERFLOW) of the FLAGS Register being set to ‘1’ and a continuous Mark (‘1’) signal will then be

transmitted until a new value is loaded into TX DATA BYTE Register.

Tx DATA PSK signal:

tDEL

TX DATA Register loaded:

Start D0 D1 D2 D3 D4 D5 D6 D7 P'ty Stop Start D0

tLOAD

TX DATA READY flag bit:

tUFL

TX DATA UNDERFLOW flag bit:

Figure 6: Transmit UART Function (Async)

Received data from the PSK Demodulator goes into the receive part of the UART block, where it is handled in

one of two ways depending on the setting of bit 5 of the UART MODE Register:

1. If bit 5 of the UART MODE Register is ‘0’ (‘Sync’ mode) then the receive part of the UART block will

simply take 8 consecutive bits from the Demodulator and transfer them to the RX DATA BYTE Register

(the first bit going into the D0 position).

2. If bit 5 of the UART MODE Register is ‘1’ (‘Async’ mode) then the received data output of the PSK

Demodulator is treated as asynchronous characters each comprising:

A Start bit (Space).

7 or 8 Data bits as determined by bit 0 of the UART MODE Register. These bits will be placed into the

RX DATA BYTE Register with the first bit received going into the D0 position.

An optional Parity bit as determined by bits 1 and 2 of the UART MODE Register. If Parity is enabled

(bit 2 of the UART MODE Register = ‘1’) then bit 7 of the FLAGS Register will be set to ‘1’ if the

received parity is incorrect.

Any number of Stop bits (Mark).

2000 MX-COM, Inc.

www.mxcom.com tel: 800 638 5577 336 744 5050 fax: 336 744 5054

Doc. # 20480197.006

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