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AD568K

12-Bit Ultrahigh Speed Monolithic D/A Converter

Analog Devices 

DIGITAL GROUND CLOCK

PLANE

INPUT

WORDS

5V

ANALOG GROUND

PLANE

+15V

–15V

OUTPUT

5V

AD568

SETTLING/GLITCH

EVALUATION BOARD

AD568

High-Speed Interconnect and Routing

It is essential that care be taken in the signal and power ground

circuits to avoid inducing extraneous voltage drops in the signal

ground paths. It is suggested that all connections be short and

direct, and as physically close to the package as possible, so that

the length of any conduction path shared by external compo-

nents will be minimized. When runs exceed an inch or so in

length, some type of termination resistor may be required. The

necessity and value of this resistor will be dependent upon the

logic family used.

For maximum ac performance, the DAC should be mounted di-

rectly to the circuit board; sockets should not be used as they in-

troduce unwanted capacitive coupling between adjacent pins of

the device.

Component Side

ANALOG VCC

ANALOG VEE

ANALOG +5V

+5V

Applications

1 ␮s, 12-BIT SUCCESSIVE APPROXIMATION A/D

CONVERTER

The AD568’s unique combination of high speed and true 12-bit

accuracy can be used to construct a 12-bit SAR-type A/D con-

verter with a sub-µs conversion time. Figure 19 shows the con-

figuration used for this application. A negative analog input

voltage is converted into current and brought into a summing

junction with the DAC current. This summing junction is

bidirectionally clamped with two Schottky diodes to limit its

voltage excursion from ground. This voltage is differentially am-

plified and passed to a high-speed comparator. The comparator

output is latched and fed back to the successive approximation

register, which is then clocked to generated the next set of codes

for the DAC.

Foil Side

Figure 18. Printed Circuit Board Layout

+15V

VI N

–15V 0 TO –10.24V

0.2µF

+5V –5V

2.5k –5V

COMPARATOR

LT1016

+5V

24 VCC

12 GND

Q11 21

Q10 20

2 D0 SAR Q9 19

23 Q11 2504 Q8 18

10 NC

Q7 17

15 NC

Q6 16

22 NC

Q5 9

13 CP

Q4 8

1E

14 S

3 CC

11 D

Q3 7

Q2 6

Q1 5

Q0 4

1

+15V 24

0.1µF

2

REFCOM 23

0.1µF

3

–15V 22

4

IBPO 21

5 DAC IOUT 20

6 AD568 RL 19

7

ACOM 18

8

LCOM 17

9

SPAN 16 NC

10

SPAN 15 NC

11

THCOM 14

100pF

12

VTH 13

1k

0.1µF

1k

0.01µF

620

620

150

Q3

1k

D3

IN4148

Q1 Q2

1 V+

2 +IN

3 –IN

4 V–

OUT 8

OUT 7

GND 6

LCH 5

D1

D2

ANALOG

GND PLANE

+5V

27k

–15V

15kΩ

Q4

150kΩ

INVERTER

74HC04

PARALLEL DATA

OUT

150kΩ

Q5

+5V

CONVERSION COMPLETE

START COMVERT

CHIP ENABLE

REV. A

Figure 19. AD568 1 µs Successive Approximation A/D Application

–11–

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