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AD568

12-Bit Ultrahigh Speed Monolithic D/A Converter

Analog Devices 

AD568–SPECIFICATIONS (@ = +25؇C, VCC, VEE = ؎15 V unless otherwise noted)

Model

AD568J

Min Typ Max

AD568K

Min Typ Max

AD568S

Min Typ

Max

RESOLUTION

ACCURACY1

Linearity

TMIN to TMAX

Differential Nonlinearity

TMIN to TMAX

Monotonicity

Unipolar Offset

Bipolar Offset

Bipolar Zero

Gain Error

TEMPERATURE COEFFICIENTS2

Unipolar Offset

Bipolar Offset

Bipolar Zero

Gain Drift

Gain Drift (IOUT)

DATA INPUTS

Logic Levels (TMIN to TMAX)

VIH

VIL

Logic Currents (TMIN to TMAX)

IIH

IIL

VTH Pin Voltage

CODING

CURRENT OUTPUT RANGES

VOLTAGE OUTPUT RANGES

COMPLIANCE VOLTAGE

12

12

12

–1/2

+1/2

–1/4

+1/4

–1/2

+1/2

–3/4

+3/4

–1/2

+1/2

–3/4

+3/4

–1

+1

–1/2

+1/2

–1

+1

–1

+1

–1

+1

–1

–1

GUARANTEED OVER RATED SPECIFICATION TEMPERATURE RANGE

–0.2

+0.2

*

*

*

*

–1.0

+1.0

*

*

*

*

–0.2

+0.2

*

*

*

*

–1.0

+1.0

*

*

*

*

–5

+5

–3

+3

–5

+5

–30

+30

–20

+20

–30

+30

–15

+15

•

•

•

•

–50

+50

–30

+30

–50

+50

–150

+150

*

*

*

*

2.0

7.0

0.0

0.8

–10

0

+10

–0.5 –60 –100

1.4

–2

+1.2

*

*

*

*

*

*

*

*

*

*

*

*

*

*

*

BINARY, OFFSET BINARY

0 to 10.24, ± 5.12

0 to 1.024, ± 0.512

*

*

*

*

–100

*

*

*

*

–200

*

OUTPUT RESISTANCE

Exclusive of RL

160

200 240

*

*

Inclusive of RL

99

100 101

*

*

SETTLING TIME

Current to

± 0.025%

35

*

*

± 0.1%

23

*

*

Voltage

50 Ω Load3, 0.512 V p-p,

to 0.025%

37

*

*

to 0.1%

25

*

*

to 1%

18

*

*

75 Ω Load3, 0.768 V p-p,

to 0.025%

40

*

*

to 0.1%

25

*

*

to 1%

20

*

*

100 Ω (Internal RL)3, 1.024 V p-p,

to 0.025%

50

*

*

to 0.1%

38

*

*

to 1%

24

*

*

Glitch Impulse4

350

*

*

Peak Amplitude

15

*

*

FULL-SCALE TRANSlTlON5

10% to 90% Rise Time

11

*

*

90% to 10% Fall Time

11

*

*

POWER REQUIREMENTS

+13.5 V to +16.5 V

–13.5 V to –16.5 V

Power Dissipation

PSRR

27

32

–7

–8

525 625

0.05

*

*

*

*

*

*

*

*

*

*

*

*

*

*

TEMPERATURE RANGE

Rated Specification2

0

+70

0

Storage

–65

+150

*

+70

–55

*

*

NOTES

*Same as AD568J.

1Measured in IOUT mode.

2Measured in VOUT mode, unless otherwise specified. See text for further information.

3Total Resistance. Refer to Figure 3,

4At the major carry, driven by HCMOS logic. See text for further explanation.

5Measured in VOUT mode.

Specifications shown in boldface are tested on all production units at final electrical test.

Specifications subject to change without notice.

+125

*

–2–

Units

Bits

LSB

LSB

LSB

LSB

% of FSR

% of FSR

% of FSR

% of FSR

ppm of FSR/°C

ppm of FSR/°C

ppm of FSR/°C

ppm of FSR/°C

ppm of FSR/°C

V

V

µA

µA

V

mA

V

V

Ω

Ω

ns to 0.025% of FSR

ns to 0.1% of FSR

ns to 0.025% of FSR

ns to 0.1% of FSR

ns to 1% of FSR

ns to 0.025% of FSR

ns to 0.1% of FSR

ns to 1% of FSR

ns to 0.025% of FSR

ns to 0.1% of FSR

ns to 1% of FSR

pV-sec

% of FSR

ns

ns

mA

mA

mW

% of FSR/V

°C

°C

REV. A

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