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AD568KQ/883B Datasheet PDF : 14 Pages
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AD568
sation capacitor across the 1 kΩ feedback resistor produces opti-
mal settling. Lower noise gain can be achieved by connecting RL
to IOUT, increasing the DAC output impedance to approximately
200 Ω, and reducing the noise gain to 6 (illustrated in Figure 9).
While the output in this configuration will feature improved
noise performance, it is somewhat less stable and may suffer
from ringing. The compensation capacitance should be in-
creased to 7 pF to maintain stability at this reduced gain.
+15V –15V
0.2µF
Noninverting Configuration
If a positive full-scale output voltage is required, it can be imple-
mented using the AD568 in the unbuffered voltage output mode
followed by the AD840 in a noninverting configuration (Figure
10). The noise gain of this topology is 10, requiring only 5 pF
across the feedback resistor to optimize settling.
+15V –15V
0.2µF
0.1µF
0.1µF
DIGITAL
INPUTS
1
+15V 24
0.1µF
2
REFCOM 23
3
–15V 22 0.1µF
4
IBPO 21
5
IOUT 20
6 AD568 RL 19
7
ACOM 18
8
LCOM 17
9
SPAN 16
5pF
10
SPAN 15
11
THCOM 14
100pF
12
VTH 13
RTH
1kΩ
–VS
100Ω
+VS
AD840
ANALOG
OUTPUT
ANALOG
GND PLANE
ANALOG
SUPPLY
GROUND
DIGITAL
GND PLANE
DIGITAL
SUPPLY
GROUND
AMPLIFIER NOISE GAIN: 11
+5V
Figure 8. Unipolar Output Buffered 0 to –10.24V
+15V
–15V
0.2µF
0.1µF
DIGITAL
INPUTS
1
+15V 24
0.1µF
2
REFCOM 23
3
–15V 22 0.1µF
4
IBPO 21
5
IOUT 20
6 AD568 RL 19
7
ACOM 18
8
LCOM 17
9
SPAN 16
7pF
10
SPAN 15
11
THCOM 14
100pF
12
VTH 13
RTH
1kΩ
–VS
200Ω
+VS
AD840
ANALOG
OUTPUT
ANALOG
GND PLANE
ANALOG
SUPPLY
GROUND
DIGITAL
GND PLANE
DIGITAL
SUPPLY
GROUND
AMPLIFIER NOISE GAIN: 6
+5V
Figure 9. Bipolar Output Buffered ±5.12 V
Bipolar Inverting Configuration
Figure 9 illustrates the implementation of a +5.12 V to –5.12 V
bipolar range, achieved by connecting the bipolar offset current,
IBPO, to the summing junction of the external amplifier. Note
that since the amplifier is providing an inversion, the full-scale
output voltage is –5.12 V, while the bipolar offset voltage (all
bits OFF) is +5.12 V at the amplifier output.
DIGITAL
INPUTS
1
+15V 24
0.1µF
2
REFCOM 23
3
–15V 22 0.1µF
4
IBPO 21
5
IOUT 20
6 AD568 RL 19
111Ω
7
ACOM 18
8
LCOM 17
9
SPAN 16
5pF
10
SPAN 15
11
THCOM 14
100pF
12
VTH 13
RTH
1kΩ
–VS +VS
AD840
ANALOG
OUTPUT
ANALOG
GND
PLANE
ANALOG
SUPPLY
GROUND
DIGITAL GND PLANE
DIGITAL
SUPPLY
GROUND
AMPLIFIER NOISE GAIN: 10
+5V
Figure 10. Unipolar Output Buffered 0 V to +10.24 V
Guidelines for Using the AD568
The designer who seeks to combine high speed with high preci-
sion faces a challenging design environment. Where tens of
milliamperes are involved, fractions of an ohm of misplaced
impedance can generate several LSBs of error. Increasing
bandwidths make formerly negligible parasitic capacitances and
inductances significant. As system performance reaches and ex-
ceeds that of the measurement equipment, time-honored test
methods may no longer be trustworthy. The DAC’s placement
on the boundary between the analog and digital domains intro-
duces additional concerns. Proper RF techniques must be used
in board design, device selection, supply bypassing, grounding,
and measurement if optimal performance is to be realized. The
AD568 has been configured to be relatively easy to use, even in
some of the more treacherous applications. The device charac-
teristics shown in this data sheet are readily achievable if proper
attention is paid to the details. Since a solid understanding of
the circuit involved is one of the designer’s best weapons against
the difficulties of RF design, the following sections provide illus-
trations, explanations, examples, and suggestions to facilitate
successful design with the AD568.
Current Output vs. Voltage Output
As indicated in Figures 3 through 10, the AD568 has been
designed to operate in several different modes depending on the
external circuit configuration. While these modes may be
categorized by many different schemes, one of the most impor-
tant distinctions to be made is whether the DAC is to be used to
generate an output voltage or an output current. In the current
output mode, the DAC output (Pin 20) is tied to some type of
summing junction, and the current flowing from the DAC into
this summing junction is sensed (e.g., Figures 8 and 9). In this
–6–
REV. A
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