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AD568KQ

12-Bit Ultrahigh Speed Monolithic D/A Converter

Analog Devices 

AD568

and well matched. The glitch-sensitive user should be equally

diligent about minimizing the data skew at the AD568’s inputs,

particularly for the 4 or 5 most significant bits. This can be

achieved by using the proper logic family and gate to drive the

DAC, and keeping the interconnect lines between the logic out-

puts and the DAC inputs as short and as well matched as pos-

sible, particularly for the most significant bits. The top 6 bits

should be driven from the same latch chip if latches are used.

Glitch Reduction Schemes

BIT-DESKEWING—Even carefully laid-out boards using the

proper driving logic may suffer from some degree of data-skew

induced glitch. One common approach to reducing this effect is

to add some appropriate capacitance (usually several pF) to

each of the 2 or 3 most significant bits. The exact value of each

capacitor for a given application should be determined experi-

mentally, as it will be dependent on circuit board layout and the

type of driving logic used. Table II presents a few examples of

how the glitch impulse may be reduced through passive

deskewing.

Table II. Bit Delay Glitch Reduction Examples1

Logic

Family

Gate

Uncompensated Compensation Compensated

Glitch

Used

Glitch

HCMOS 74157 350 pV-s

STTL 74158 850 pV-s

C2 = 5 pF

R1 = 50 Ω,

C1 = 7 pF

250 pV-s

600 pV-s

NOTE

1Measurements were made using a modified version of the fixture shown in

Figure 13, with resistors and capacitors placed as shown in Figure 15. Resis-

tance and capacitance values were set to zero except as noted.

As Figure 15 indicates, in some cases it may prove useful to

place a few hundred ohms of series resistance in the input line

to enhance the delay effect. This approach also helps to reduce

some of the digital feedthrough glitch, as the higher frequency

spectral components are being filtered out of the most signifi-

cant bits’ digital inputs.

R – C BIT DESKEWING SCHEME

R1

1 BIT 1 (MSB)

FROM

R2

DRIVING

LOGIC

R3

2 BIT 2

3 BIT 3

AD568

4 BIT 4

5 BIT 5

6 BIT 6

Figure 15. R-C Bit Deskewing Scheme

THRESHOLD SHIFT—It is also possible to reduce the data

skew by shifting the level of logic voltage threshold, VTH (Pin

13). This can be readily accomplished by inserting some resis-

tance between the THRESHOLD COM pin (Pin 14) and

ground, as in Figure 16. To generate threshold voltages below

1.4 V, Pin 13 may be directly driven with a voltage source, leav-

ing Pin 14 tied to the ground plane. As Note 2 in Table III indi-

cates, lowering the threshold voltage may reduce output voltage

compliance below the specified limits, which may be of concern

in an unbuffered voltage output topology.

AD568

THCOM 14

VTH 13

RB

C1: 1000pF CHIP CAPACITOR

C1

RA

ANALOG

GROUND

PLANE

+5V

Figure 16. Positive Threshold Voltage Shift

Table III shows the glitch reduction achieved by shifting the

threshold voltage for HCMOS, STTL, and FAST logic.

Table III. Threshold Shift for Glitch Improvement1

Logic

Family

Gate

Uncompensated Modified

Resulting

Glitch

Threshold2 Glitch

HCMOS 74HC158 350 pV-s

STTL 74S158 850 pV-s

FAST 74F158 1000 pV-s

1.7 V

1.0 V

1.3 V

150 pV-s

200 pV-s

480 pV-s

NOTES

1Measurements made on a modified version of the circuit shown in Figure 13,

with a 1 V full scale.

2Use care in any scheme that lowers the threshold voltage since the output volt-

age compliance of the DAC is sensitive to this voltage. If the DAC is to be op-

erating in the voltage output mode, it is strongly suggested that the threshold

voltage be set at least 200 mV above the output voltage full scale.

Deglitching

Some applications may prove so sensitive to glitch impulse that

reduction of glitch impulse by an order of magnitude or more is

required. In order to realize glitch impulses this low, some sort

of sample-and-hold amplifier (SHA)-based deglitching scheme

must be used.

There are high-speed SHAs available with specifications suffi-

cient to deglitch the AD568, however most are hybrid in design

at costs which can be prohibitive. A high performance, low cost

alternative shown in Figure 17 is a discrete SHA utilizing a

high-speed monolithic op amp and high-speed DMOS FET

switches.

This SHA circuit uses the inverting integrator architecture. The

AD841 operational amplifier used (300 MHz gain bandwidth

product) is fabricated on the same high-speed process as the

AD568. The time constant formed by the 200 Ω resistor and the

100 pF capacitor determines the acquisition time and also band

limits the output signal to eliminate slew induced distortion.

A discrete drive circuit is used to achieve the best performance

from the SD5000 quad DMOS switch. This switch driving cell

is composed of MPS571 RF npn transistors and an MC10124

TTL to ECL translator. Using this technique provides both

high speed and highly symmetrical drive signals for the SD5000

switches. The switches are arranged in a single-throw double-

pole (SPDT) configuration. The 360 pF “flyback” capacitor is

switched to the op amp summing junction during the hold mode

to keep switching transients from feeding to the output. The ca-

pacitor is grounded during sample mode to minimize its effect

on acquisition time.

REV. A

–9–

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