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ST5451D

ISDN HDLC AND GCI CONTROLLER

STMicroelectronics 

ST5451

NON GCI INTERFACE

NAME

PIN

DOUT

15

DIN

12

CLK

11

FS

13

DEN

10

TYPE

O

I

I

I

I

FUNCTION

Data output. Digital output for serial data. Three modes:

- HDLC Protocol multiplexed link

- HDLC Protocol non multiplexed link

- Non HDLC protocol (transparent Mode).

Data input. Digital input for serial data. Three modes (See DOUT).

Data Clock. It determines the data shift rate. Two modes: Single or

double bit rate.

Frame synchronization. Used in mode HDCL protocol multiplexed

link. Don’t care in other modes. The rising edge gives the time

reference of the first bit of the frame.

Data Enable. When high, enable the data transfer. on DOUT

OTHERS

NAME

PIN

VDD

28

VSS

14

RST

16

ST

9

TYPE

I

I

I

I

FUNCTION

Positive power supply = 5V +5%

Signal ground

Reset

Special Test. (Reserved) must be tied to VSS

2 - FUNCTIONS

2 - 1 - Basic HDLC Functions

2 - 1 - 1 - In Receive Direction:

- Channel selection

In GCI channel B1 or B2 or D may be selected.

B1 or B2 may be selected without M and C/I

channels

- Flag detection

A zero followed by six consecutive ones and an-

other zero is recognized as a flag

- Zero delete

A zero, after five consecutive ones within an

HDLC frame, is deleted

- CRC checking

The CRC field is checked according to the gen-

erator polynomial

X16 + X12 + X5 + 1

- Check for abort

Seven or more consecutive ones are interpreted

as an abort flag

- Check for idle

Fifteen or more consecutive ones are inter-

preted as ”idle”

- Minimum lenght checking

HDLC frames with less than n bytes between

start and end flag are ignored: allowed val-

ues are 3 ≤ n ≤ 6.

This value is set by a programmable register

- Address Field recognition

4 SAPI and/or 3 TEI may be recognized. Sev-

eral programmable registers indicate the recog-

nized address types.

2 - 1 - 2 - In Transmit Direction:

- Shift control in TE mode

D channel data are signalled by DEN pin.

- Flag generation

A flag is generated at the beginning and at the

end of every frame.

- Zero insert

A zero is inserted after five consecutive ones

within an HDLC frame

- CRC generation

The CRC field of the transmitted frame is gener-

ated according to the generator polynomial

X16 + X12 + X5 + 1

- Abort sequence generation

An HDLC frame may be terminated with an

abort sequence under microprocessor control

- Interframe time fill

Flags or idle (consecutive ones) may be trans-

mitted during the interframe time. A programma-

ble bit selects the mode.

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