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ST78C36

ECP/EPP PARALLEL PRINTER PORT WITH 16-BYTE FIFO

Exar Corporation 

ST78C36/36A

REV. 5.1.0

ECP/EPP PARALLEL PRINTER PORT WITH 16-BYTE FIFO

4.0 DEVICE OPERATION

4.1 SPP MODE

This is ECR mode 000 (system RESET mode).

In this output-only mode the host data is registered to PD[7:0] at the trailing edge of -IOW; PDIR is driven low;

-STROBE, -AUTOFD, INIT, and -SLCTIN are open-drain; and all timing is managed by the host through DSR

and DCR registers.

4.2 PS2 MODE

This is ECR mode 001.

In this bi-directional mode the host output data is registered to PD[7:0] at the trailing edge of -IOW, PDIR is

driven by DIR to allow peripheral data input, -AUTOFD, INIT, and -SLCTIN are totem-pole, and all timing is

managed by the host through DSR and DCR registers.

4.3 PPF MODE

This is ECR mode 010.

In this output-only mode the host data is written to the FIFO with I/O writes to address 400 or by DMA writes;

PDIR is driven low; -AUTOFD, INIT, and -SLCTIN are totem-pole.

FIFO data is automatically registered to PD[7:0] whenever the FIFO-E bit is low (data available), and timing is

generated by controller logic that handshakes -STROBE (controller) with BUSY (peripheral).

4.4 ECP MODE

This is ECR mode 011.

In this bi-directional mode the host data is written to the FIFO with I/O writes to address 000, 400 or DMA;

PDIR is driven by DIR (can only be set in ECR mode 001); -AUTOFD, INIT, and -SLCTIN are totem-pole. I/O

writes to address 000 will write a low into the FIFO tag bit, while I/O writes to address 400 or DMA will insert a

high.

4.4.1 ECP FORWARD MODE (PDIR = 0)

FIFO data is automatically registered to PD[7:0] whenever the FIFO-E bit is low (data available), and timing is

generated by controller logic that handshakes -STROBE (controller) with BUSY (peripheral). Data from the

FIFO tag bit is output on -AUTOFD after being registered simultaneous with FIFO data.

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