ST8004CD Ver la hoja de datos (PDF) - STMicroelectronics
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ST8004CD Datasheet PDF : 19 Pages
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ST8004
DATA LINES (PINS I/O, AUX1 AND AUX2 WITH 10 kΩ PULL-UP RESISTOR CONNECTED TO VCC
INTERNALLY (VDD = 3.3V, VDDP = 5V, fXTAL = 10MHz, unless otherwise noted. Typical values are to
Ta = 25°C)
Symbol
Parameter
Test Conditions
Min.
Typ.
Max. Unit
VOH High Level Output Voltage on IOH = - 40µA
data lines
No Load
VOL Low Level Output Voltage on IOL = 1 mA
data lines
VIH High Level Input Voltage on
data lines
VIL Low Level Input Voltage on
data lines
VINACTIVE
IEDGE
Voltage on data lines when
inactive
Current from data lines when
active pull-up is active
No Load
II/O = 1 mA
VOH = 0.7 x VCC; CO = 80 pF
|IIH|
IIL
RPU(INT)
tT(DI)
tT(DO)
CI
Input Leakage Current when
high
Low Level Input Current
Internal pull-up resistance to
VCC
Input transition times
Output transition times
Input capacitance
VIH = VCC
VIL = 0
From VIL max to VIH min
CO = 80 pF, no DC load;
0.4 V to 70% from 0 to VCC
0.75 VCC
0.9 VCC
1.8
-0.3
-1
9
VCC
V
VCC+0.3
300
mV
VCC
V
0.8
V
0.1
V
0.3
mA
10
µA
600
µA
13
KΩ
1
µs
0.1
µs
10
pF
DATA LINES (PINS I/OUC, AUX1UC AND AUX2UC WITH 10 kΩ PULL-UP RESISTOR CONNECTED
TO VDD INTERNALLY (VDD = 3.3V, VDDP = 5V, fXTAL = 10MHz, unless otherwise noted.
Typical values are to Ta = 25°C)
Symbol
Parameter
Test Conditions
Min.
Typ.
Max. Unit
VOH High Level Output Voltage IOH = - 40µA
0.75 VDD
No Load
0.9 VDD
VOL Low Level Output Voltage IOL = 1 mA
0
VIH High Level Input Voltage
0.7 VDD
VIL Low Level Input Voltage
0
|ILIH|
Input Leakage Current when VIH = VDD
high
IIL
Input Leakage Current when VIL = 0
low
RPU(INT) Internal pull-up resistance to
VDD
9
11
tT(DI) Input transition times
From VIL max to VIH min
tT(DO) Output transition times
CO = 30 pF, no DC load; 10% to
90% from 0 to VDD
CI
Input capacitance
VDD
V
300
mV
VDD
V
0.3 VDD
V
10
µA
600
µA
13
KΩ
1
µs
0.1
µs
10
pF
6/19
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